3D Semiconductor Memory Vertical Stacking Integration
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Solution Overview
Problem
Current semiconductor memory devices face challenges in increasing integration levels and capacity while maintaining reliable charge accumulation and threshold voltage stability, particularly in three-dimensional configurations.
Innovation Solution
A semiconductor memory device with a stacked structure comprising control gate electrodes, a semiconductor layer, and a first insulating layer, where part of the insulating layer acts as a charge accumulation layer and an oxide layer, positioned between the semiconductor layer and the control gate electrodes, with a specific configuration that suppresses the influence on the drain side select gate transistor and allows for easy manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are disposed three-dimensionally to raise integration level, then capacity and integration level are improved, but manufacturing complexity and reliability control become more difficult
Solution Approach 1:
The patent transitions from planar two-dimensional memory cell arrangement to three-dimensional vertical stacking, where multiple memory cell layers are stacked above a substrate. This dimensional change enables higher integration levels by utilizing the vertical space, allowing more memory cells to be packed into a smaller footprint area while maintaining manufacturability through standardized layer-by-layer fabrication processes.
2Reliability
If charge accumulation layer is used to store data, then nonvolatile storage capability is improved, but threshold voltage stability and reliability become more challenging to maintain
Solution Approach 1:
The patent employs a composite insulating layer structure consisting of a charge accumulation layer (first insulating layer) and an oxide layer (second insulating layer). The charge accumulation layer stores data by accumulating charges, while the oxide layer provides electrical isolation and stabilizes the threshold voltage by preventing charge leakage and interference. This composite structure simultaneously achieves nonvolatile storage capability and threshold voltage stability.
3Stability of the object's composition
If oxide layer is added to isolate charge accumulation layer, then threshold voltage stability is improved, but manufacturing steps and device complexity increase
Solution Approach 1:
The patent combines the oxide layer formation step with the existing charge accumulation layer fabrication process. The oxide layer is formed as a second insulating layer directly over the charge accumulation layer using the same manufacturing sequence, integrating the threshold voltage stabilization function into the existing structure without requiring separate, additional manufacturing steps. This merging approach maintains threshold voltage stability while avoiding increased device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the stability of the threshold voltage and reduces fluctuations, allowing for higher integration levels and capacity while simplifying the manufacturing process.
Implementation Method 1
part of the first insulating layer is a charge accumulation layer
Data Source
AI summary
According to an embodiment, a semiconductor memory device comprises a plurality of control gate electrodes, a semiconductor layer, and a first insulating layer. The plurality of control gate electrodes are stacked above a substrate. The semiconductor layer has as its longitudinal direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The first insulating layer is positioned between the semiconductor layer and the control gate electrode. In addition, part of the first insulating layer is a charge accumulation layer. Moreover, part of the first insulating layer is an oxide layer positioned upwardly of the charge accumulation layer.