3D Semiconductor Memory Device Vertical Stacking Integration
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Solution Overview
Problem
Conventional two-dimensional semiconductor devices have limited integration density due to high costs associated with miniaturization, necessitating the development of three-dimensional semiconductor memory devices with improved electrical characteristics and reliability.
Innovation Solution
A three-dimensional semiconductor memory device is designed with semiconductor patterns having a horizontal portion and a vertical portion, where the horizontal portion is thinner than the vertical portion, and is connected to a bit line and a gate electrode, enhancing electrical characteristics and reliability through increased contact area and efficient layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional semiconductor memory devices are used to increase integration density, then integration density is improved, but manufacturing complexity increases
Solution Approach 1:
The patent transitions from two-dimensional planar device architecture to three-dimensional vertical stacking architecture. Memory cells are arranged in multiple stacked layers rather than expanded horizontally, enabling increased integration density by utilizing the vertical dimension. This dimensional change allows more memory cells to be packed into a smaller footprint area.
Solution Approach 2:
The semiconductor pattern is divided into distinct functional segments: a vertical portion extending upward from the substrate and a horizontal portion extending laterally. This segmentation allows each portion to serve specific functions - the vertical portion for vertical interconnection and the horizontal portion for lateral connection to bit lines, simplifying the overall manufacturing process despite the 3D structure.
2Quantity of substance
If the horizontal portion thickness is reduced to improve integration density, then integration density is improved, but contact area between semiconductor pattern and silicide pattern is reduced
Solution Approach 1:
The patent compensates for the reduced horizontal thickness by extending the vertical portion height. The vertical portion provides additional contact area through its extended height, creating a longer contact interface with the silicide pattern. This dimensional compensation ensures adequate contact area even when the horizontal thickness is minimized for higher integration density.
Solution Approach 2:
Different portions of the semiconductor pattern are designed with different thickness characteristics - the horizontal portion has minimal thickness for compact integration, while the vertical portion has extended height for adequate contact. This local differentiation of geometric properties allows each region to optimize for its specific function.
3Reliability
If vertical portion height is increased to improve contact area, then reliability is improved, but device height increases
Solution Approach 1:
The vertical portion is designed with selective thickness variation - thicker at the contact region with the silicide pattern to maximize contact area, and thinner at other regions. This localized thickness optimization provides adequate contact area without uniformly increasing the entire device height, achieving reliability improvement with minimal height penalty.
Data Source
AI summary
A semiconductor memory device may include at least one semiconductor pattern including a horizontal portion extending in a second direction parallel to a top surface of a semiconductor substrate and a vertical portion extending in the first direction, at least one gate electrode on the horizontal portion of the at least one semiconductor pattern and extending in a third direction different from the first direction and the second direction, and at least one information storage element connected to the vertical portion of the at least one semiconductor pattern, wherein a thickness of the horizontal portion of the at least one semiconductor pattern in the first direction is smaller than a thickness of the vertical portion of the at least one semiconductor pattern in the first direction.