3D Semiconductor Memory Vertical Transistor Layout
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Solution Overview
Problem
As the degree of integration in semiconductor memory devices with two-dimensional structures reaches its limit, the increasing number of transistors for coupling memory cells to peripheral circuit elements leads to increased area occupation, hindering further miniaturization.
Innovation Solution
A semiconductor memory device with a three-dimensional structure is designed, featuring a memory cell array with vertically stacked gate lines and transistors that overlap with the peripheral circuit elements, reducing the area occupied by transistors and enabling a more compact layout by using vertical channels and gate dielectric layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the degree of integration is increased in a three-dimensional semiconductor memory device, then the integration density is improved, but the area occupied by transistors for coupling memory cells to peripheral circuit elements increases
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional vertical structure. Transistors are configured with gate electrodes extending in the first direction (vertical direction) perpendicular to the substrate, allowing current to flow vertically through vertical channels. This dimensional change enables higher integration density without proportionally increasing the planar area occupied by transistors, as multiple transistor functions are achieved within the vertical stack rather than requiring lateral expansion.
2Adaptability or versatility
If more transistors are added to couple memory cells to peripheral circuit elements, then the functionality is improved, but the overall device size increases
Solution Approach 1:
The patent merges multiple transistor functions into a shared vertical structure. Multiple gate lines are stacked vertically and coupled to a common peripheral circuit element through shared vertical channels and gate electrodes. This consolidation allows multiple coupling functions to be achieved within a compact vertical footprint rather than requiring separate lateral transistor instances for each coupling function, thereby maintaining versatility while reducing overall device volume.
Solution Approach 2:
The patent implements a nested structure where gate lines are stacked vertically one above another, with each gate line surrounded by insulation layers and coupled to vertical channels. The vertical channels are nested within the three-dimensional structure, passing through multiple gate line layers. This nesting arrangement enables multiple coupling functions to be packed into a compact volume by utilizing the vertical dimension, thereby reducing the overall device size while maintaining full coupling functionality.
Data Source
AI summary
A semiconductor memory device includes a peripheral circuit element provided over a lower substrate; an upper substrate provided over an interlayer dielectric layer which partially covers the peripheral circuit element; a memory cell array including a channel structure which extends in a first direction perpendicular to a top surface of the upper substrate and a plurality of gate lines which are stacked over the upper substrate to surround the channel structure; and a plurality of transistors electrically coupling the gate lines to the peripheral circuit element. The transistors include a gate electrode provided over the interlayer dielectric layer and disposed to overlap with the memory cell array in the first direction; a plurality of vertical channels passing through the gate electrode in the first direction and electrically coupled to the gate lines, respectively; and gate dielectric layers disposed between the vertical channels and the gate electrode.