3D Semiconductor Memory Device Wafer Bonding Integration
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Solution Overview
Problem
The challenge lies in achieving low-cost, mass-production of three-dimensional (3D) semiconductor memory devices that maintain or exceed the operational reliability of their two-dimensional (2D) counterparts, as conventional methods face manufacturing obstacles and require expensive equipment for further integration.
Innovation Solution
A semiconductor device is fabricated with a peripheral circuit structure on a first substrate, a cell array structure on top, and a second substrate interposed between them, featuring a stacked structure with through holes and vertical semiconductor patterns, including gate electrodes and insulating layers, to enhance integration density and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional (3D) memory cell arrays are adopted to increase device integration, then integration density is improved, but manufacturing complexity and cost increase due to significant manufacturing obstacles and expensive equipment requirements
Solution Approach 1:
The device is divided into separate modules: a first substrate with peripheral circuit structure, a second substrate with cell array structure, and an interposed substrate. This segmentation allows each module to be fabricated independently using conventional processes, then combined through wafer bonding, thereby achieving high integration density without proportionally increasing manufacturing complexity
Solution Approach 2:
A second substrate is introduced as an intermediary between the peripheral circuit structure on the first substrate and the cell array structure. This intermediary substrate facilitates the combination of 2D peripheral circuits with 3D memory cells through wafer bonding, enabling complex 3D integration while maintaining manufacturing feasibility
2Quantity of substance
If three-dimensional (3D) memory cell arrays are adopted to increase device integration, then integration density is improved, but production cost increases due to expensive process equipments needed
Solution Approach 1:
By segmenting the device into separately fabricable modules (peripheral circuit substrate, cell array substrate, and interposed substrate), each can be manufactured using conventional, cost-effective processes rather than requiring expensive specialized 3D fabrication equipment
Solution Approach 2:
The invention uses wafer bonding to replicate and combine multiple substrate structures, allowing mass production of high-density 3D devices through copying and stacking of conventionally fabricated wafers, thereby reducing per-unit cost
3Ease of manufacture
If conventional 2D memory cell arrays are used to maintain manufacturing simplicity, then ease of manufacture is preserved, but device integration remains limited
Solution Approach 1:
The invention transitions from conventional two-dimensional memory cell arrays to a three-dimensional architecture by stacking the cell array structure vertically above the peripheral circuit structure, with the second substrate serving as the interposing layer, thereby achieving higher integration density while maintaining manufacturing simplicity through conventional fabrication processes
Solution Approach 2:
The device is divided into separate modules: a first substrate with peripheral circuit structure, a second substrate with cell array structure, and an interposed substrate. This segmentation allows each module to be fabricated independently using conventional processes, then combined through wafer bonding, thereby achieving high integration density without proportionally increasing manufacturing complexity
4Quantity of substance
If 3D semiconductor memory devices are fabricated to achieve high integration, then integration density is improved, but operational reliability becomes difficult to maintain
Solution Approach 1:
By dividing the device into separately fabricable modules with clear functional separation (peripheral circuits on first substrate, memory cells on second substrate), each module can be optimized and tested independently, then combined through reliable wafer bonding to maintain overall operational reliability
Solution Approach 2:
The second substrate serves as an intermediary that provides mechanical support and electrical connection between the peripheral circuit structure and cell array structure, ensuring stable signal transmission and maintaining operational reliability in the 3D configuration
Data Source
AI summary
A semiconductor device is provided as follows. A peripheral circuit structure is disposed on a first substrate. A cell array structure is disposed on the peripheral circuit structure. A second substrate is interposed between the peripheral circuit structure and the cell array structure. The cell array structure includes a stacked structure, a through hole and a vertical semiconductor pattern. The stacked structure includes gate electrodes stacked on the second substrate. The through hole penetrates the stacked structure and the second substrate to expose the peripheral circuit structure. The vertical semiconductor pattern is disposed on the peripheral circuit structure, filling the through hole.