3D Stacked Semiconductor Memory Wiring Lines
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Solution Overview
Problem
The integration of semiconductor memory devices is limited by the complexity of two-dimensional structures, which restricts the number of wiring lines that can be efficiently routed without causing electrical interference and signal distortion due to coupling capacitance with bit lines.
Innovation Solution
A semiconductor memory device with a three-dimensional structure, where gate lines and wiring lines are stacked over a substrate, with specific step structures and extended portions to accommodate more wiring lines within a limited area, reducing the need for additional planar space and minimizing signal distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a two-dimensional planar structure is used for semiconductor memory devices, then the device structure is simple and easy to manufacture, but the degree of integration is limited due to the area occupied by unit memory cells and wiring lines
Solution Approach 1:
The patent transitions from a two-dimensional planar structure to a three-dimensional stacked structure. Multiple gate lines and wiring lines are arranged in different vertical layers (first gate lines in a first layer, second gate lines in a second layer, etc.), allowing memory cells to be stacked vertically. This dimensional change dramatically increases the degree of integration without requiring additional planar area, as wiring lines and memory cells are distributed across multiple height levels rather than competing for the same surface space.
2Quantity of substance
If the size of memory cell decreases to increase integration, then the degree of integration increases, but the structures of operating circuits and wiring lines become increasingly complicated
Solution Approach 1:
By stacking wiring lines and memory cell arrays in different vertical layers, the patent reduces the complexity of interconnections. Instead of routing numerous wiring lines across a large planar area (which becomes complex as cell size decreases), the three-dimensional structure allows wiring lines to be organized in vertical columns and layers, simplifying the routing topology and reducing the number of cross-overs and interconnections required in the planar domain.
Solution Approach 2:
The patent divides the memory device into multiple stacked layers, with each layer containing specific gate lines and memory cell arrays. This segmentation allows independent design and optimization of each layer, reducing the overall complexity by breaking down the monolithic two-dimensional structure into manageable three-dimensional modules that can be fabricated and assembled systematically.
3Adaptability or versatility
If more wiring lines are routed in a two-dimensional plane, then the connectivity increases, but electrical interference and signal distortion due to coupling capacitance with bit lines increases
Solution Approach 1:
The patent resolves electrical interference issues by routing wiring lines in different vertical layers rather than densely packing them in the same planar layer. The first gate lines are positioned in a first layer while second gate lines are positioned in a second layer at a different height, physically separating potentially interfering signal paths. This vertical separation reduces parasitic coupling capacitance between adjacent wiring lines and bit lines, maintaining signal integrity while achieving high connectivity across multiple memory cell arrays.
Data Source
AI summary
A semiconductor memory device includes gate lines and wiring lines which are stacked over a substrate. The gate lines are stacked over first and second cell array regions of a substrate which are disposed in a second direction crossing with a first direction, and are passed through by channel structures. The wiring lines are stacked over an interval region of the substrate which is disposed between the first and second cell array regions and over first coupling regions of the substrate which are disposed at both sides of the first and second cell array regions and the interval region in the first direction. Each of the wiring lines includes a line portion which traverses the interval region in the first direction and extended portions which are disposed over the first coupling regions. A width of the extended portions is larger than a width of the line portion.