Semiconductor Device Reinforcing Metal Layer Thermal Stress

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Solution Overview

Problem

Semiconductor devices face damage due to thermal stress applied to electrode terminals, which can lead to cracks in the printed wiring substrate, particularly at the boundary lines between the electrode terminals and pads, causing structural integrity issues.

Innovation Solution

A semiconductor device configuration that includes a reinforcing metal layer on the electrode pad, straddling the boundary line between the electrode terminal and pad, which helps distribute thermal stress and reduce its impact on the substrate, thereby minimizing crack formation and maintaining structural integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If electrode terminals are mounted on the printed wiring substrate, then electrical connection is achieved, but thermal stress causes cracks at the boundary lines between electrode terminals and pads

Engineering Contradiction:
Improvestructural integrityVSAvoidthermal stress
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies a reinforcing metal layer specifically at the boundary lines between electrode terminals and pads, rather than uniformly across the entire substrate. This localized reinforcement addresses the specific stress concentration points where cracks occur, improving reliability without adding unnecessary weight or complexity elsewhere in the structure.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent uses a composite structure combining the printed wiring substrate with a reinforcing metal layer (such as copper or aluminum) at critical boundary regions. This composite approach leverages the electrical properties of the substrate while adding the mechanical strength of the metal layer to resist thermal stress and prevent cracking.

Inventive Principle:
Principle #40Composite materials

2Strength

If a reinforcing metal layer is applied to strengthen electrode terminals, then resistance to thermal stress improves, but manufacturing complexity increases

Engineering Contradiction:
Improvethermal stress resistanceVSAvoidmanufacturing process
Core Design Contradiction:
StrengthVSDevice complexity

Solution Approach 1:

The reinforcing metal layer is segmented to be applied only at the specific boundary lines between electrode terminals and pads, rather than as a continuous layer. This segmentation reduces the amount of material required and simplifies the manufacturing process while still providing effective reinforcement at the critical stress points.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The reinforcing metal layer is applied locally only where thermal stress concentration occurs (at the boundary lines), rather than uniformly across the entire electrode terminal area. This localized application reduces manufacturing complexity and material costs while maintaining adequate strength where it is most needed.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20230178491A1Semiconductor device
Publication Date: 2023.06.08 KIOXIA CORP
  • US20230178491A1 patent drawing
  • US20230178491A1 patent drawing
  • US20230178491A1 patent drawing

AI summary

A semiconductor device includes: a printed wiring substrate; a semiconductor chip mounted on a first surface of the printed wiring substrate; a sealing resin sealing the semiconductor chip on the first surface of the printed wiring substrate; an electrode pad provided on a second surface on a side opposite to the first surface of the printed wiring substrate; an electrode terminal connected to the electrode pad and protruding from the second surface; and a metal layer provided on a surface of the electrode pad on the electrode terminal side or on the side opposite to the electrode terminal so as to straddle a boundary line of the bonding surface between the electrode terminal and the electrode pad which is at least a boundary line on a side facing an outside of a mounting region of the semiconductor chip.