Semiconductor Device Metal Layer Resistance Reduction
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Solution Overview
Problem
Semiconductor devices, such as MOSFETs, face challenges in reducing ON-resistance due to high electrical resistance components in the metal layer and n+-type semiconductor layer, which also lead to manufacturing inefficiencies and wafer warp issues.
Innovation Solution
A semiconductor device design featuring a metal layer between the substrate and semiconductor body, with a contact layer and metal bonding layer to reduce electrical resistance and prevent wafer warp, while maintaining efficient manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a metal layer is used in the semiconductor device, then electrical conductivity is improved, but electrical resistance in the metal layer remains high
Solution Approach 1:
The patent uses a composite metal layer structure combining CuAl alloy and TiN layer. The CuAl alloy provides low electrical resistance while the TiN layer prevents aluminum diffusion and enhances adhesion. This composite structure resolves the contradiction by achieving both low electrical resistance and high reliability through material composition rather than single material optimization.
Solution Approach 2:
The patent optimizes the thickness parameters of each metal layer (CuAl alloy layer: 50-200 nm, TiN layer: 5-50 nm) to achieve the desired electrical conductivity while minimizing resistance. By precisely controlling layer thickness parameters, the device achieves optimal electrical performance without excessive resistance.
2Reliability
If the metal layer thickness is increased to reduce resistance, then electrical conductivity improves, but manufacturing complexity and cost increase
Solution Approach 1:
The patent divides the metal layer into multiple thin segments (CuAl alloy layer and TiN layer) rather than using a single thick layer. This segmentation achieves the required electrical conductivity through combined effect of multiple thin layers, reducing manufacturing complexity compared to depositing a single thick metal layer while maintaining low resistance.
Solution Approach 2:
The composite metal layer structure with specific thickness ratios allows each layer to perform its optimized function at reduced thickness, simplifying the overall manufacturing process while achieving the desired electrical performance through material composition rather than relying on increased total thickness.
3Ease of manufacture
If standard metal layers are used, then manufacturing process is simple, but ON-resistance remains high
Solution Approach 1:
The patent changes the material parameters from standard aluminum or copper to CuAl alloy with specific composition ratios and controlled thickness. This parameter change reduces ON-resistance while maintaining compatibility with existing semiconductor manufacturing processes, achieving both low resistance and manufacturing ease.
Solution Approach 2:
The composite CuAl alloy and TiN layer structure provides low ON-resistance while using deposition techniques compatible with standard semiconductor manufacturing. The structure achieves superior electrical performance without requiring fundamentally new manufacturing equipment or processes.
Data Source
AI summary
A semiconductor device includes a substrate, a semiconductor body and a metal layer between the substrate and the semiconductor body. The device further includes first and second electrodes, a first control electrode between the semiconductor body and the first electrode; and a second control electrode between the semiconductor body and the second electrode. The semiconductor body includes a first to fifth semiconductor layers. The second semiconductor layer is provided between the first semiconductor layer and the first electrode. The third semiconductor layer is selectively provided between the second semiconductor layer and the first electrode. The fourth semiconductor layer is provided between the first semiconductor layer and the second electrode. The fifth semiconductor layer selectively provided between the fourth semiconductor layer and the second electrode. The first, third and fifth semiconductor layers are of a first conductivity type. The second and fourth semiconductor layers are of a second conductivity type.