Semiconductor Module Compact Design via Asymmetric Element Layout
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Solution Overview
Problem
Conventional semiconductor modules are larger in size due to unnecessary circuit patterns on the conductor foil and face constraints in heat dissipation efficiency due to limited arrangement and orientation of power semiconductor elements.
Innovation Solution
A semiconductor module design featuring a first circuit substrate with insulating and conductive layers, a second circuit substrate with embedded wiring layers, and lead terminals that eliminate the need for circuit patterns where semiconductor elements are not mounted, allowing for a more compact size and improved heat dissipation by optimizing the arrangement and orientation of semiconductor elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If circuit patterns are formed on the conductor foil to connect all electrodes, then electrical connectivity is ensured, but the module size increases due to unnecessary patterns where semiconductor elements are not mounted
Solution Approach 1:
The patent extracts and eliminates unnecessary circuit patterns from the conductor foil, specifically removing patterns in regions where semiconductor elements are not mounted. This reduces the overall area occupied by circuit patterns while maintaining essential electrical connectivity through optimized pattern placement only where needed.
Solution Approach 2:
The patent transitions from a two-dimensional planar arrangement of all circuit patterns on the conductor foil to a more efficient layout that utilizes vertical stacking and selective positioning. By arranging semiconductor elements and their corresponding circuit patterns in optimized positions, the design reduces the horizontal footprint while maintaining all necessary electrical connections.
2Device complexity
If power semiconductor elements are arranged on the conductor foil with fixed constraints, then electrical connections are simplified, but heat dissipation efficiency deteriorates due to limited arrangement and orientation options
Solution Approach 1:
The patent employs asymmetric arrangement of power semiconductor elements on the conductor foil, allowing different orientations and positions for different elements. This asymmetric layout optimizes heat dissipation paths and thermal contact with the heat dissipation substrate, while the conductor foil's flexible circuit pattern design accommodates these varied positions without increasing connection complexity.
Solution Approach 2:
The patent applies local quality optimization by providing enhanced thermal contact mechanisms specifically at the interface between power semiconductor elements and the heat dissipation substrate. The conductor foil's circuit patterns are locally adapted to each semiconductor element's position and orientation, allowing optimal electrical and thermal performance for each component while maintaining overall system simplicity.
3Ease of manufacture
If conventional substrate materials are used, then manufacturing is straightforward, but warping occurs due to thermal expansion differences, affecting module flatness and reliability
Solution Approach 1:
The patent employs a composite substrate structure consisting of a heat dissipation substrate with specific thermal and mechanical properties, combined with a conductor foil layer. This composite construction balances thermal expansion characteristics between layers, reducing warping while maintaining manufacturability. The heat dissipation substrate serves as a stable base that compensates for thermal stresses in the conductor foil.
Solution Approach 2:
The patent modifies the thermal and mechanical parameters of the substrate system by selecting materials with matched thermal expansion coefficients and optimized thickness ratios. The heat dissipation substrate's properties are specifically chosen to counteract warping tendencies of the conductor foil during thermal cycling, while the overall structure remains compatible with conventional manufacturing processes.
Data Source
AI summary
A semiconductor module includes: a first circuit substrate having a conductive layer disposed on an insulating plate; a plurality of semiconductor elements on the conductive layer, a second circuit substrate disposed above the semiconductor elements, the second circuit substrate having a main current wiring layer and a control wiring layer positioned in a layer above the main current wiring layer; a first lead terminal vertically extending upwards from and in contact with the main current wiring layer; a second lead terminal vertically extending upwards from and in contact with the conductive layer of the first circuit substrate; a third lead terminal vertically extending upwards from and in contact with the control wiring layer; and a sealing material covering at least some of the elements mentioned above.