Semiconductor Module Flux Cancellation Layout
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Solution Overview
Problem
Conventional semiconductor modules face challenges in reducing parasitic inductance, which leads to surge voltages and malfunctions due to limitations in layout options and chip downsizing, making it difficult to form layouts that reduce parasitic inductance effectively.
Innovation Solution
The semiconductor module design includes electronic devices with specific current directions and wiring configurations to cancel magnetic fluxes, using parallel current flows and regulation currents to minimize mutual inductance, thereby reducing parasitic inductance and surge voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If chip size is reduced to downsize the semiconductor module, then the module size is reduced, but layout options are limited making it difficult to reduce parasitic inductance
Solution Approach 1:
The patent transitions from planar layout to three-dimensional stacked arrangement of chips. Multiple chips are arranged in vertical layers with wiring lines extending through intermediate substrates, enabling current paths to flow in opposite directions in different layers. This dimensional change provides the adaptability needed to reduce parasitic inductance while maintaining compact module size.
2Quantity of substance
If chips are downsized to increase quantity mounted, then more devices can be mounted, but layout flexibility is reduced preventing effective parasitic inductance reduction
Solution Approach 1:
The semiconductor module is divided into multiple independent chip layers mounted on intermediate substrates. Each chip can be independently positioned and connected, allowing flexible arrangement of current paths. This segmentation enables mounting more devices while maintaining layout flexibility to create opposing current flows that reduce parasitic inductance.
Solution Approach 2:
By stacking chips in multiple vertical layers with wiring lines passing through intermediate substrates, the patent creates three-dimensional current paths. This allows opposing current directions to be achieved in different layers, providing the layout flexibility needed to reduce parasitic inductance while accommodating multiple downsized chips.
3Ease of manufacture
If conventional layout is used with limited options, then manufacturing is simpler, but parasitic inductance cannot be appropriately reduced leading to surge voltages
Solution Approach 1:
The patent uses vertical stacking with wiring lines extending through intermediate substrates to create three-dimensional current paths. This allows current to flow in opposite directions in different layers, effectively reducing parasitic inductance. The modular layered structure maintains manufacturing simplicity while achieving superior electrical performance.
4Reliability
If current flows in opposite directions is attempted to reduce parasitic inductance, then mutual inductance is reduced, but layout becomes difficult with downsized chips
Solution Approach 1:
The patent achieves opposing current flows by arranging chips in vertical layers with wiring lines extending through intermediate substrates. Current flows in one direction in lower layers and in the opposite direction in upper layers, creating magnetic flux cancellation. This three-dimensional arrangement provides the layout versatility needed to implement opposite current directions with downsized chips.
Solution Approach 2:
By dividing the module into multiple chip layers on separate intermediate substrates, the patent enables independent routing of current paths in each layer. This segmentation allows current to flow in opposite directions in different layers, reducing mutual inductance while maintaining layout flexibility for downsized chips.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces parasitic inductance and associated surge voltages, maintaining compact size and enabling the mounting of multiple devices while preventing malfunctions.
Implementation Method 1
the first electronic device and the second electronic device are arranged so that at least part of a first magnetic flux generated by the first device current flowing in the first current direction cancels at least part of a second magnetic flux generated by the second device current flowing in the second current direction to reduce mutual inductance
Data Source
AI summary
A semiconductor module includes a first electronic device in which one terminal is connected to a first wiring line, the other terminal is connected to a second wiring line, and a first device current flows in a first current direction from the first wiring line to the second wiring line, and a second electronic device in which one terminal is connected to a third wiring line, the other terminal is connected to a fourth wiring line, and a second device current flows in a second current direction from the third wiring line to the fourth wiring line, the first electronic device and the second electronic device being disposed such that at least part of a first magnetic flux generated by the first device current flowing in the first current direction cancels at least part of a second magnetic flux generated by the second device current.