Semiconductor Module Gate-Source Inductance Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In power semiconductor modules, high-speed switching demands require minimizing wiring inductance and its fluctuations to prevent semiconductor element deterioration, particularly for gate-source wiring to enhance switching speed and reliability.
Innovation Solution
A semiconductor module design featuring parallel gate and source terminals with relay layers and adjacent wiring configurations to reduce gate-source inductance fluctuations, incorporating a layout where gate and source wires are adjacent and connected through relay layers, and main wiring layers are disposed in parallel with the case member's side walls to minimize inductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-speed switching is implemented to reduce switching loss, then switching speed improves, but surge voltage increases due to wiring inductance causing semiconductor element deterioration
Solution Approach 1:
The patent transitions from planar wiring layout to a three-dimensional stacked configuration where gate wires and source wires are arranged in different layers (first wiring layer and second wiring layer). This vertical dimensionality change allows the wires to be closely coupled while maintaining electrical isolation, effectively reducing inductance without increasing planar footprint.
Solution Approach 2:
The patent merges the gate wire and source wire into a closely coupled pair structure where they extend in substantially the same direction and are positioned adjacent to each other. This merging approach creates a differential pair configuration that reduces loop area and minimizes inductance, directly addressing the surge voltage issue while enabling high-speed switching.
2Loss of energy
If wiring inductance is reduced to enable high-speed switching, then switching loss decreases, but inductance fluctuations between chips increase affecting reliability
Solution Approach 1:
The patent segments the wiring into distinct first and second wiring layers, with gate wires in one layer and source wires in another. This segmentation allows independent optimization of each wire's path and positioning, ensuring consistent inductance characteristics across multiple chips while maintaining low overall inductance for reduced switching loss.
Solution Approach 2:
The patent applies local quality by making the gate wire and source wire have substantially the same length and extending them in the same direction in specific local regions. This localized control of wire geometry ensures consistent inductance values across different chip instances, improving reliability while maintaining low switching loss.
3Speed
If gate-source wiring inductance is minimized to increase switching speed, then switching performance improves, but wiring complexity increases
Solution Approach 1:
The patent uses vertical stacking of wiring layers to achieve complex three-dimensional wire routing that would be difficult to implement in a single planar layer. This approach minimizes gate-source inductance for high-speed switching while managing wiring complexity through structured layering rather than chaotic planar routing.
Data Source
AI summary
A semiconductor module includes a case with a side wall in a first direction in which gate and source terminals are embodied and exposed therefrom, first and second semiconductor elements each having gate and source electrodes, gate and source relay layers positioned at a center between the first and second semiconductor elements in the first direction at a side of the semiconductor elements farther from the side wall, first gate and source wires respectively connecting the gate and source terminals to the gate and source relay layers, second gate and source wires, and third gate and source wires, respectively connecting the gate and source electrodes of the first semiconductor element, and the gate and source electrode of the second semiconductor element, to the gate and source relay layers. The first to third source wires are respectively located closer to the first to third gate wires than any other gate wires.