Power Semiconductor Module Mirror Symmetry Wiring
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In power semiconductor modules used in large-current and high-voltage applications, current unbalance occurs between multi-parallel connected power semiconductor elements, leading to potential breakage due to surge voltages, and existing solutions fail to adequately reduce inductance while maintaining insulation distance.
Innovation Solution
The power semiconductor module incorporates substrates with different wiring patterns arranged in mirror symmetry to connect self-arc-extinguishing type semiconductor elements, reducing current unbalance and maintaining low inductance by ensuring identical current directions in adjacent wiring patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple power semiconductor modules are connected in parallel to satisfy current capacity requirements, then the current capacity is improved, but the footprint increases due to required insulation distance between modules
Solution Approach 1:
The patent combines multiple power semiconductor modules into a single integrated package, merging functions that were previously distributed across separate modules. This integration eliminates the need for external insulation distances while maintaining electrical isolation through internal insulating structures, thereby reducing footprint while preserving current capacity.
Solution Approach 2:
The patent transitions from a two-dimensional layout with modules arranged on a plane (requiring insulation distance) to a three-dimensional integrated structure where modules are stacked or arranged vertically within a single package. This dimensional change allows closer spacing and reduced footprint while maintaining required insulation through internal design.
2Area of stationary object
If power semiconductor elements are arranged in multi-parallel array within the same package to reduce footprint, then the footprint is reduced, but the inductance reduction effect is insufficient and current unbalance occurs
Solution Approach 1:
The patent introduces asymmetric current path designs and non-uniform wiring patterns within the integrated package to compensate for parasitic inductance variations. By deliberately creating asymmetric compensation paths, the system balances the overall current distribution across parallel elements, preventing current unbalance while maintaining compact footprint.
Solution Approach 2:
The patent optimizes wiring pattern parameters such as trace width, spacing, and routing geometry to minimize parasitic inductance differences between parallel current paths. By carefully adjusting these parameters, the system achieves uniform current distribution across multi-parallel elements without requiring large insulation distances.
3Device complexity
If external terminals are integrated into one terminal to reduce module complexity, then device complexity is reduced, but inductance increases and current unbalance occurs
Solution Approach 1:
The patent segments the integrated terminal into multiple internal connection paths that diverge from a single external terminal. This segmentation allows the external terminal to remain simple while internally distributing current through multiple low-inductance paths to parallel power semiconductor elements, thereby maintaining low inductance without increasing external complexity.
Solution Approach 2:
The patent implements a nested structure where multiple internal wiring patterns are contained within the footprint of a single external terminal. The terminal serves as an outer container that houses multiple concentric or layered current paths, allowing complex internal routing to be achieved without increasing external terminal count or complexity.
Data Source
AI summary
A power semiconductor module includes: a positive arm and a negative arm that are formed by series connection of self-arc-extinguishing type semiconductor elements, the positive arm and the negative arm being connected at a series connection point between the self-arc-extinguishing type semiconductor elements; a positive-side electrode, a negative-side electrode, and an AC electrode connected to the positive arm and the negative arm; and a substrate on which a plurality of wiring patterns are formed, the wiring patterns connecting the self-arc-extinguishing type semiconductor elements of the positive arm and the negative arm to the positive-side electrode, the negative-side electrode, and the AC electrode. Respective directions of current flowing in adjacent wiring patterns are identical to each other, and one of the adjacent wiring patterns is arranged in mirror symmetry with the other of the adjacent wiring patterns.