Semiconductor Module Surge Voltage Absorption Layout
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Solution Overview
Problem
Existing semiconductor modules fail to reliably reduce surge voltage between the positive-side and negative-side input terminals of power conversion circuits due to the elongated distance between transistors and snubber capacitors, leading to insufficient voltage absorption.
Innovation Solution
A semiconductor module design where the absorbing-device connecting area is situated between the first-transistor and second-transistor mounting areas, allowing the absorbing device to be close to both transistors, thereby reducing wire inductance and effectively lowering surge voltage, and incorporating capacitors to stabilize voltage and enhance capacitance for better voltage tolerance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If the snubber capacitor is placed separately from the transistor mounting area, then thermal separation is achieved to prevent heat degradation, but the distance between the capacitor and transistor increases, resulting in insufficient surge voltage reduction
Solution Approach 1:
The insulating substrate is divided into distinct functional areas: a first mounting area for transistors, a second mounting area for the snubber capacitor, and a connecting area with patterns. This segmentation allows thermal separation while maintaining electrical connection through optimized interconnection paths.
Solution Approach 2:
The insulating substrate acts as an intermediary between the transistor and snubber capacitor, providing both thermal isolation and electrical connection. The substrate's insulating properties prevent heat transfer while its conductive patterns enable signal and power transmission.
2Object-affected harmful factors
If the distance between the transistor and snubber capacitor is reduced, then surge voltage absorption is improved, but thermal separation is compromised, leading to heat degradation
Solution Approach 1:
Different regions of the insulating substrate are assigned different functional qualities: the first mounting area is optimized for transistor attachment with appropriate thermal characteristics, while the second mounting area is optimized for capacitor attachment. The connecting area has specific electrical conductivity properties to minimize inductance while maintaining thermal isolation.
Solution Approach 2:
The problem is solved by transitioning from a one-dimensional proximity metric to a two-dimensional spatial arrangement. The capacitor and transistor are positioned in separate areas on the substrate plane, with electrical connection achieved through optimized trace routing rather than direct physical proximity.
3Object-affected harmful factors
If the wire inductance is reduced by placing the absorbing device closer to the transistor, then surge voltage is effectively reduced, but the layout complexity increases
Solution Approach 1:
The insulating substrate serves multiple functions simultaneously: it provides mechanical support for mounting components, thermal isolation between hot and cold areas, electrical insulation, and signal transmission pathways. This multi-functionality reduces the need for additional components or complex interconnection structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces surge voltage by minimizing wire inductance and stabilizing voltage, ensuring reliable power conversion and improved performance, especially with faster switching speeds in wide-bandgap semiconductor materials.
Implementation Method 1
a snubber capacitor serving as a surge voltage absorbing device is placed between the positive-side input terminal and the negative-side input terminal
Data Source
AI summary
A semiconductor module according to an embodiment includes an insulating substrate having a power conversion circuit mounted thereon, a first transistor constituting an upper arm, a second transistor constituting a lower arm, a first input interconnection pattern coupled to a positive-side input terminal, a second input interconnection pattern coupled to a negative-side input terminal, an output interconnection pattern coupled to an output terminal, and an absorbing device configured to absorb surge voltage, wherein the first input interconnection pattern includes a first-transistor mounting area on which the first transistor is mounted, wherein the output interconnection pattern includes a second-transistor mounting area on which the second transistor is mounted, wherein the second input interconnection pattern includes an absorbing-device connecting area disposed between the first and second transistor mounting areas, and wherein the absorbing-device connecting area is electrically coupled to the first-transistor mounting area through the absorbing device.