Semiconductor Device Mold Layers with Rounded Interlayer Insulation
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Solution Overview
Problem
As the number of stacked gates in semiconductor devices increases, interference between information storage regions grows, affecting the degree of integration and efficiency of semiconductor devices.
Innovation Solution
A method of manufacturing semiconductor devices involves forming alternately stacked mold layers with recessed regions and interlayer insulation layers, where the interlayer insulation layers have rounded corners to reduce electric field concentration and lateral charge loss, and information storage patterns are formed on the corrugated inner side surfaces of holes passing through the stacked structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked gates is increased to improve the degree of integration, then the integration density is improved, but interference between information storage regions increases
Solution Approach 1:
The patent divides the information storage regions into vertically stacked separate regions, each isolated by interlayer insulation layers. This segmentation allows multiple storage regions to coexist without interference, resolving the contradiction between increasing integration density and preventing regional interference.
Solution Approach 2:
The patent transitions from planar information storage to vertical stacking in the third dimension. By forming information storage patterns at different heights through stacked mold layers and interlayer insulation layers, the patent achieves higher integration density while maintaining isolation between storage regions through vertical stratification.
2Ease of manufacture
If conventional flat interlayer insulation layers are used, then the manufacturing process is simple, but electric field concentration and lateral charge loss occur
Solution Approach 1:
The patent forms rounded corners on the interlayer insulation layers instead of sharp angles. This curvature prevents electric field concentration at corner regions, reducing lateral charge loss and improving device reliability while maintaining manufacturing feasibility through modified etching or deposition processes.
3Ease of manufacture
If holes with straight inner side surfaces are formed, then the etching process is straightforward, but gap-fill characteristics are poor
Solution Approach 1:
The patent forms holes with corrugated or rounded inner side surfaces instead of straight vertical walls. This curved geometry improves gap-fill characteristics by allowing better material distribution and contact during subsequent deposition processes, enhancing manufacturing precision while the corrugated pattern can be achieved through controlled etching.
Data Source
AI summary
A hole is formed to pass through preliminary first mold layers and preliminary second mold layers to form first mold layers and mold layers respectively that are alternately stacked in a vertical direction, perpendicular to a lower structure, on the lower structure. The first mold layers are partially etched along a side surface of the hole to form recess regions and recessed first mold layers. Third mold layers are formed in the recess regions to form interlayer insulation layers so that each of the interlayer insulation layers includes a corresponding third mold layer and a corresponding recessed first mold layer that are positioned at the same level in the vertical direction. A first dielectric layer is formed in the hole to cover the third mold layers and the second mold layers stacked on each other. Information storage patterns are formed on the first dielectric layer.