Semiconductor Neural Circuit with Oxide Analog Memory Refresh
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Solution Overview
Problem
Existing semiconductor devices for neural networks face challenges in achieving reduced chip area, lower power consumption, and flexible hierarchical structure configurations due to the complexity of digital and analog memory, multiplier, and adder circuits, particularly in high-definition imaging and data processing applications.
Innovation Solution
A semiconductor device incorporating a first circuit for signal amplification and conversion, a second circuit with analog memory and multiplier, and a third circuit for signal generation and difference calculation, utilizing transistors with oxide semiconductors to reduce chip area and power consumption, and enable flexible circuit configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If digital circuits are used for memory, multiplier, and adder circuits, then processing capability is improved, but circuit configuration becomes large and manufacturing precision requirements increase
Solution Approach 1:
The patent replaces digital electronic circuits with a hybrid analog-digital circuit system. Specifically, the memory circuit and multiplier circuit are implemented using analog circuits (capacitors and transistors), while the adder circuit uses digital logic. This substitution reduces the overall circuit configuration size and manufacturing precision requirements compared to fully digital implementation, while maintaining processing capability.
2Device complexity
If analog memory is used to store connection strength, then circuit size is reduced, but data retention time becomes extremely short
Solution Approach 1:
The patent implements a refresh mechanism that periodically restores the analog memory data. The control circuit detects when the analog memory data needs refreshing and periodically applies refresh signals to maintain the data without requiring large capacitors or continuous power consumption, thus solving the short data retention time issue while keeping circuit size small.
3Duration of action of stationary object
If large capacitor is implemented in analog memory to extend data retention, then data retention time is improved, but chip area increases
Solution Approach 1:
Instead of using large capacitors to extend data retention time, the patent employs periodic refresh operations controlled by a control circuit. This approach maintains adequate data retention time using smaller capacitors, thereby avoiding chip area increase while still solving the data retention problem.
4Duration of action of stationary object
If periodic refresh operations are performed to recover analog data, then data retention is improved, but power consumption increases
Solution Approach 1:
The patent implements refresh operations that are periodic rather than continuous, and only activates when needed based on control circuit detection. This reduces power consumption compared to continuous refresh schemes while still maintaining data retention, as the refresh operations are performed at optimal intervals rather than constantly.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables a semiconductor device with reduced chip area, lower power consumption, and adaptable hierarchical structures, enhancing performance in high-definition imaging and data processing tasks.
Implementation Method 1
The analog memory includes a transistor that includes an oxide semiconductor in a channel formation region
Implementation Method 2
The first circuit includes a first function of amplifying a first signal and output the first signal to the second circuit, and a second function of converting the first signal from current to voltage
Implementation Method 3
The second circuit includes a first multiplier circuit that changes data corresponding to a connection strength, an analog memory that stores the data, and a second multiplier circuit that outputs a second signal that is obtained by weighting of the first signal
Data Source
AI summary
A neuron circuit can switch between two functions: as an input neuron circuit, and as a hidden neuron circuit. An error circuit can switch between two functions: as a hidden error circuit, and as an output neuron circuit. A switching circuit is configured to be capable of changing the connections between the neuron circuit, a synapse circuit, and the error circuit. The synapse circuit includes an analog memory that stores data that corresponds to the connection strength between the input neuron circuit and the hidden neuron circuit or between the hidden neuron circuit and the output neuron circuit, a writing circuit that changes the data in the analog memory, and a weighting circuit that weights an input signal in reaction to the data of the analog memory and outputs the weighted output signal. The analog memory includes a transistor comprising an oxide semiconductor with extremely low off-state current.