Semiconductor Noise Suppression via High Loss Dielectric Layer
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Solution Overview
Problem
The increased operation speed and reduced size of semiconductor devices lead to challenges in suppressing simultaneous switching noise and maintaining signal integrity and power integrity, particularly due to the difficulty in ensuring sufficient area for power-supply and ground planes and arranging bypass capacitors, especially when signal wiring is present on these layers.
Innovation Solution
A semiconductor device configuration with a substrate featuring a ground plane and power-supply plane separated by a dielectric layer, where a high dielectric loss tangent layer is positioned between the edges of the planes, offset in the orthogonal direction, effectively suppressing noise without attenuating signal wiring by increasing transmission loss at high frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the area of power-supply plane or ground plane is enlarged to suppress simultaneous switching noise, then noise suppression is improved, but device size increases and density decreases
Solution Approach 1:
The patent applies local quality by providing a via hole with conductive filling material at specific locations where power-supply planes and ground planes face each other, rather than uniformly enlarging the entire planes. This localized approach suppresses noise at critical points while maintaining compact device dimensions.
Solution Approach 2:
The via hole with conductive filling material acts as an intermediary element between the power-supply plane and ground plane. It provides a localized conductive path that suppresses simultaneous switching noise without requiring the planes themselves to be enlarged, thus resolving the contradiction between noise suppression and device size.
2Object-affected harmful factors
If bypass capacitors are mounted to reduce noise between power supply and ground, then noise suppression is improved, but device area increases
Solution Approach 1:
The patent extracts the noise suppression function from discrete bypass capacitors and integrates it directly into the substrate structure via via holes with conductive filling material. This eliminates the need for separate capacitor components, reducing device area while maintaining noise suppression effectiveness.
Solution Approach 2:
The patent merges the noise suppression function with the substrate structure itself by forming via holes with conductive filling material between power-supply planes and ground planes. This integration combines multiple functions (structural support and noise suppression) into a single element, reducing the overall device area.
3Speed
If operation speed is increased, then device performance is improved, but simultaneous switching noise increases
Solution Approach 1:
The patent implements preliminary action by pre-forming via holes with conductive filling material in the substrate during manufacturing, before the device operates at high speeds. This proactive structural preparation ensures noise suppression pathways are already in place to handle the increased simultaneous switching noise generated by high-speed operation.
Solution Approach 2:
The patent addresses noise suppression by transitioning from a two-dimensional plane approach (enlarging power-supply and ground planes) to a three-dimensional approach (forming via holes with conductive filling material that extend vertically between planes). This dimensional change enables effective noise suppression at high operating speeds without increasing the footprint area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration efficiently reduces simultaneous switching noise across a wide frequency range, ensuring signal integrity and power integrity by effectively managing noise between the power supply and ground planes, even when signal wiring is integrated on the power supply layer or ground layer.
Implementation Method 1
a high dielectric loss tangent layer having a higher tan δ than the periphery is provided in the dielectric layer
Data Source
AI summary
A high dielectric loss tangent layer is provided in a dielectric layer between a power-supply plane and a ground plane. The high dielectric loss tangent layer is arranged such that its edge is located between the edge of the power-supply plane and the edge of the ground plane. The edge of the high dielectric loss tangent layer is preferably separated by a predetermined distance or more from the edge of the power-supply plane or the edge of the ground plane which is located on the inner side.