Semiconductor Package with Non-Stepped Vertical Conductive Structure

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Solution Overview

Problem

Conventional semiconductor packages face issues of high cost, decreased reliability, and large package sizes, leading to suboptimal performance.

Innovation Solution

A method for manufacturing semiconductor devices involves creating a substrate with a dielectric structure and conductive structure, including a conductor tier with non-stepped sidewalls, where the conductor is exposed from both the top and bottom surfaces of the dielectric layer, and an encapsulant contacts the electronic component laterally, facilitating efficient integration and reduced package size.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If conventional semiconductor packaging methods are used, then manufacturing processes are complex and costly, but package size is large and reliability is decreased

Engineering Contradiction:

Improvemanufacturing process simplicityVSAvoidpackage size

Core Design Contradiction:

Ease of manufactureVSVolume of stationary object

Solution Approach 1:

The patent combines conductor formation and via formation into a single etching process. The conductive structure includes conductors and vias formed simultaneously in one dielectric layer through dual-pattern etching, eliminating the need for separate via formation steps and reducing manufacturing complexity while maintaining compact package size

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent uses non-stepped sidewalls in the conductive structure where the sidewall extends vertically from the top surface to the bottom surface of the dielectric layer without horizontal steps. This vertical integration approach reduces the horizontal footprint and package size while simplifying the manufacturing process

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Ease of manufacture

If conventional semiconductor packaging methods are used, then manufacturing processes are complex, but reliability is decreased

Engineering Contradiction:

Improvemanufacturing process simplicityVSAvoidpackage reliability

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent merges conductor and via formation into a single integrated process where both features are created in one etching step. This reduces the number of process steps and potential failure points, thereby improving reliability while simplifying manufacturing

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent inverts the conventional approach by forming non-stepped sidewalls that extend vertically without horizontal segments. This inversion of the traditional stepped structure reduces stress concentrations and improves structural reliability while simplifying the manufacturing process

Inventive Principle:

Principle #13The other way round (Inversion)

3Volume of stationary object

If conventional semiconductor packaging methods are used, then package size is large, but performance is suboptimal

Engineering Contradiction:

Improvepackage sizeVSAvoiddevice performance

Core Design Contradiction:

Volume of stationary objectVSReliability

Solution Approach 1:

The patent transitions from horizontal conductor routing to vertical conductor routing with non-stepped sidewalls. This vertical arrangement reduces the horizontal package footprint while maintaining or improving electrical performance through shorter current paths and reduced parasitic effects

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent combines multiple functional elements (conductors, vias, and interconnects) into a single integrated conductive structure within one dielectric layer. This integration reduces package size while improving performance through reduced signal path length and lower resistance

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS20230121621A1Semiconductor devices and methods of manufacturing semiconductor devices

Publication Date: 2023.04.20 AMKOR TECH SINGAPORE HLDG PTE LTD

AI summary

In one example, an electronic device comprises a substrate having a top side and a bottom side, an electronic component over the top side of the substrate, and an encapsulant over the top side of the substrate. The substrate comprises a dielectric structure comprising a first dielectric layer and a conductive structure in the dielectric structure and comprising a first conductor tier in the first dielectric layer comprising a first trace exposed from a top side of the first dielectric layer and partially extending through the first dielectric layer and a first via exposed from the top side of the first dielectric layer and a bottom side of the first dielectric layer and extending from the top side of the first dielectric layer to the bottom side of the first dielectric layer. The first trace and the first via have non-stepped sidewalls extending vertically. Other examples are also disclosed herein.