Semiconductor Device Stacking with Overlapping Lead Frames
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Solution Overview
Problem
The challenge in semiconductor device design is to stack multiple chips without increasing the package thickness, as existing technologies result in a thicker device due to the positioning of child chips relative to parent chips and the use of thin metal wires for connections.
Innovation Solution
The solution involves stacking a first semiconductor chip on a first island and a second semiconductor chip on a second island, with the islands partially overlapping to reduce the overall package thickness, using lead frames with specific configurations and electrical connections to maintain separation and reduce the occupied area, allowing for efficient stacking without increasing thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a child chip is stacked on a parent chip using thin metal wires for connection, then electrical connection between chips is achieved, but the package thickness is increased
Solution Approach 1:
The patent transitions from vertical stacking (increasing thickness) to horizontal overlapping arrangement of lead frames. By positioning the child chip's lead frame to overlap with the parent chip's lead frame in the planar direction rather than strictly vertically stacking chips, the connection is achieved without proportionally increasing package thickness.
Solution Approach 2:
The child chip's lead frame is nested within the projection area of the parent chip's lead frame. The inner leads of the child chip are positioned within the region occupied by the outer leads of the parent chip, allowing compact integration without increasing the overall package footprint or thickness significantly.
2Area of stationary object
If multiple chips are stacked to reduce occupied area, then device miniaturization is achieved, but package thickness increases
Solution Approach 1:
The patent redistributes the stacking problem from the thickness dimension to the planar dimension by using overlapping lead frame arrangements. Multiple chips can be integrated by arranging their lead frames in overlapping patterns on the same or different lead frames, maintaining compact thickness while achieving area reduction.
Solution Approach 2:
The patent separates the chip stacking function into independent lead frame units that can be arranged flexibly. Each chip is mounted on its own lead frame with separate outer leads and inner leads, allowing independent positioning and overlapping arrangements to optimize both area and thickness.
Data Source
AI summary
A semiconductor device having a plurality of semiconductor chips mounted on lead frames is miniaturized by reducing its planar size and thickness. By disposing a rear surface of a first island and a top surface of a second island so as to at least partially overlap each other, a first semiconductor chip on the first island and a second semiconductor chip on a rear surface of the second island are configured so as to overlap each other. Accordingly, a planar occupied area can be set smaller than planar areas of both of the chips. Moreover, thin metal wires to be connected to the second semiconductor chip are extended to a back side. Consequently, a thickness of a semiconductor device can also be reduced.