Semiconductor Overlay Vernier via Etched Step Hard Mask
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Solution Overview
Problem
The miniaturization and increased integration of semiconductor devices require forming micro patterns, which necessitate additional process steps and increased costs due to the use of opaque amorphous carbon hard masks, necessitating additional drain key open mask and etch processes for alignment and overlay vernier measurement.
Innovation Solution
A method of forming an overlay vernier on a semiconductor substrate by etching a step and maintaining its shape with a stack layer, allowing the use of an amorphous carbon hard mask without requiring additional mask and etch processes, using a conductive layer and insulating layer to maintain the step shape for alignment and overlay vernier formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If amorphous carbon hard mask is used for micro pattern formation, then manufacturing precision is improved, but device complexity increases due to additional drain key open mask and etch processes
Solution Approach 1:
The patent merges the drain key open mask process and drain key open etch process with the overlay vernier formation process. By forming the overlay vernier pattern during the same photolithography and etching steps used for drain key opening, the patent eliminates the need for separate mask and etch processes, thereby reducing device complexity while maintaining micro pattern formation precision using amorphous carbon hard mask
Solution Approach 2:
The patent makes the overlay vernier pattern serve multiple functions: it acts as both an alignment reference for subsequent photolithography processes and as a structural feature for overlay measurement. By designing the vernier pattern to fulfill both alignment and measurement functions simultaneously, the patent reduces the number of dedicated processes needed while maintaining manufacturing precision
2Reliability
If additional drain key open mask and etch processes are performed, then alignment and overlay measurement capabilities are maintained, but production time increases
Solution Approach 1:
The patent combines the drain key open mask process and drain key open etch process with the overlay vernier formation process into a single integrated process flow. The same photolithography exposure and development steps, followed by the same etching process, are used to form both the drain key opening patterns and the overlay vernier patterns. This merging eliminates redundant process steps and reduces overall production time while maintaining alignment and overlay measurement capabilities
3Measurement precision
If additional drain key open mask and etch processes are performed, then overlay vernier measurement is enabled, but manufacturing cost increases
Solution Approach 1:
The patent merges the overlay vernier formation with the drain key open process, so that the same mask patterns and etching conditions used for drain key opening also create the overlay vernier features. This eliminates the need for separate mask fabrication, alignment, and etching processes that would be required if overlay vernier formation were performed as a distinct process, thereby reducing manufacturing cost while maintaining overlay measurement precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the process, reduces production time and cost, and enhances device reliability by eliminating the need for additional mask and etch processes, while maintaining accurate alignment and overlay vernier measurement capabilities.
Implementation Method 1
etching part of the semiconductor substrate to form a step
Data Source
AI summary
A method of manufacturing a semiconductor device in which a source contact plug and a drain contact plug are formed. The method includes the steps of etching part of the semiconductor substrate to form a step, thus forming an overlay vernier, and forming a hard mask on the step so that the step is maintained.