Semiconductor Package 3D Stacking Heat Dissipation
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Solution Overview
Problem
Current semiconductor packages face challenges in reducing the gap between components and effectively dissipating heat generated by semiconductor chips, particularly in complex and multifunctional system-in-package (SiP) designs.
Innovation Solution
The semiconductor package incorporates an interconnect structure with a redistribution pattern and vertical connection conductors, featuring a frame with through-holes for chip placement, encapsulants for chip protection, and a heat dissipation member connected to the vertical connection conductors, along with an external shielding layer for enhanced heat emission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple passive components are surface-mounted together with semiconductor components, then the package can achieve system-in-package (SiP) multifunctionality, but the gap between components cannot be reduced and the mounting area increases
Solution Approach 1:
The patent transitions from two-dimensional surface mounting to three-dimensional vertical stacking by placing passive components on the backside of the interconnect structure opposite to the semiconductor chips. This dimensional change allows simultaneous accommodation of multiple components without increasing the planar footprint, enabling SiP multifunctionality while reducing the mounting area.
2Volume of stationary object
If semiconductor chips are densely packed to reduce package size, then the package size is reduced, but heat dissipation performance deteriorates
Solution Approach 1:
The patent segments the heat dissipation function from the component mounting function by providing dedicated heat dissipation members on the backside of the interconnect structure, separate from the component placement areas. This allows dense chip packing for size reduction while maintaining effective heat dissipation paths through the interconnect structure to the heat dissipation members.
Solution Approach 2:
The interconnect structure serves as an intermediary element that simultaneously supports semiconductor chips on one surface and heat dissipation members on the opposite surface. This mediator enables close proximity of components for compact packaging while maintaining thermal management through the interconnect structure's thermal conduction to the heat dissipation members.
3Volume of stationary object
If the gap between semiconductor chips and passive components is reduced, then the package size is reduced, but electromagnetic interference increases
Solution Approach 1:
The patent places passive components on the backside of the interconnect structure, three-dimensionally separating them from semiconductor chips in the vertical dimension. This spatial separation in another dimension reduces electromagnetic interference between active and passive components while maintaining a compact overall package volume.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the size of the semiconductor package while improving heat dissipation performance, effectively managing heat from high-power semiconductor chips and reducing the mounting area for passive components.
Implementation Method 1
a heat dissipation member on the second surface of the interconnect structure and connected to the vertical connection conductor
Implementation Method 2
an external shielding layer for enhanced heat emission
Data Source
AI summary
A semiconductor package includes an interconnect structure having a first surface and a second surface opposing the first surface, and including a redistribution pattern and a vertical connection conductor, a first semiconductor chip disposed for a first inactive surface to oppose the first surface, a second semiconductor chip disposed on the first surface of the interconnect structure and disposed for the second inactive surface to oppose the first surface; a first encapsulant encapsulating the first and second semiconductor chips, a backside wiring layer disposed on the first encapsulant, a wiring structure connecting the redistribution pattern to the backside wiring layer, a heat dissipation member disposed on the second surface and connected to the vertical connection conductor.