Semiconductor Package Bonding Layout for Fine Pitch Uniformity

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Solution Overview

Problem

Existing semiconductor packages face challenges in achieving stable mounting and reliable operation due to height deviations and excessive pitch between bonding parts, limiting circuit integration and signal transmission efficiency.

Innovation Solution

A semiconductor package design with a novel structure that includes a connection member embedded in an insulating layer, featuring a first bonding part overlapping the connection member vertically and a second bonding part not overlapping, with controlled height and pitch, and a protective layer with through holes formed using a dry film pattern to minimize pitch and height deviations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the width and thickness of bonding parts are made different to accommodate connection member pads, then the connection member can be connected, but height deviation occurs between bonding parts

Engineering Contradiction:
Improveconnection member compatibilityVSAvoidbonding part height uniformity
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent applies local quality by making the protective layer thickness vary in different regions. Specifically, the protective layer has a first thickness in regions where bonding parts overlap the connection member vertically, and a second thickness (greater than the first) in regions where bonding parts do not overlap the connection member. This localized thickness variation compensates for the height differences caused by different bonding part configurations, ensuring uniform overall height across all bonding parts.

Inventive Principle:
Principle #3Local quality

2Quantity of substance

If the number of I/O terminals of the connection member increases, then more bonding parts are needed, but current intensity during plating differs causing height deviation

Engineering Contradiction:
Improvenumber of I/O terminalsVSAvoidbonding part height consistency
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patent applies parameter changes by modifying the protective layer thickness parameter in different regions. When the number of I/O terminals increases and requires more bonding parts with varying plating conditions, the protective layer thickness is adjusted as a compensating parameter. Regions with bonding parts that have different current intensities during plating are assigned different protective layer thicknesses, which equalizes the final heights of all bonding parts despite variations in plating parameters.

Inventive Principle:
Principle #35Parameter changes

3Ease of manufacture

If a pitch of at least 60 um is maintained between bonding parts, then manufacturing is easier, but circuit integration is limited

Engineering Contradiction:
Improvebonding part pitchVSAvoidcircuit integration density
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

The patent applies parameter changes by reducing the pitch between adjacent bonding parts below the conventional 60 um minimum. This is achieved through precise control of via electrode dimensions and spacing, as well as optimizing the bonding part geometry. By changing these parameters, the patent enables finer pitch bonding parts with 40 um or less spacing, thereby increasing circuit integration density while remaining manufacturable.

Inventive Principle:
Principle #35Parameter changes

4Length of stationary object

If via electrode and pad electrode widths are reduced to minimize pitch, then bonding part pitch decreases, but manufacturing precision becomes more difficult to maintain

Engineering Contradiction:
Improvebonding part pitchVSAvoidelectrode width control
Core Design Contradiction:
Length of stationary objectVSManufacturing precision

Solution Approach 1:

The patent applies parameter changes by establishing specific width ranges for via electrodes (5 um to 15 um) and pad electrodes (10 um to 20 um). These parameter specifications enable reduced bonding part pitch while maintaining manufacturability. The controlled electrode dimensions, combined with optimized spacing parameters, allow the patent to achieve fine pitch bonding parts without sacrificing manufacturing precision, as the parameters are set within ranges that balance miniaturization and fabrication capability.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20250336837A1Semiconductor package
Publication Date: 2025.10.30 LG INNOTEK CO LTD
  • US20250336837A1 patent drawing
  • US20250336837A1 patent drawing
  • US20250336837A1 patent drawing

AI summary

A semiconductor package according to an embodiment includes an insulating layer including an upper surface and a lower surface; a protective layer disposed on the upper surface of the insulating layer; a connection member embedded in the insulating layer; and a wiring electrode embedded in the insulating layer and including an upper pad part disposed between the insulating layer and the protective layer, a first via electrode electrically connected to the connection member by passing through a portion of the insulating layer from the upper pad part and having a width narrower than a width of the upper pad part; a second via electrode embedded in the insulating layer and disposed closer to a lower surface of the insulating layer than the connection member; and a bonding part including a protruding portion disposed on the protective layer and a through portion passing through the protective layer from the protruding portion and directly contacting the upper pad part, wherein the bonding part includes a first bonding part overlapping the connection member in a vertical direction, and a second bonding part not overlapping the connection member in the vertical direction, and a slope angle of each of a through portion of the first bonding part and a through portion of the second bonding part with respect to the upper surface of the insulating layer is closer to vertical than a slope angle of the second via electrode with respect to the upper surface of the insulating layer.