Semiconductor Package Layout With Cantilever Ring for Delamination Control
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Solution Overview
Problem
Semiconductor packages face issues of stress concentration and delamination due to coefficient of thermal expansion (CTE) mismatch and asymmetrical design, leading to mechanical and thermal stresses, especially around die corners, which can cause package warpage and detachment of solder bumps.
Innovation Solution
A semiconductor package design with a semiconductor device offset from the center axis and surrounded by a ring structure with a cantilevered overhang portion, combined with a lid structure covering the device, enhances bonding strength and balances material proportions to reduce stress concentration and delamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional symmetrical semiconductor package design is used, then the manufacturing process is simple, but stress concentration and delamination occur due to CTE mismatch
Solution Approach 1:
The patent applies asymmetry by offsetting the semiconductor device from the center of the substrate and designing the ring structure with a cantilevered overhang portion that extends beyond the substrate edge only on one side. This asymmetric configuration redistributes the thermal expansion stresses more evenly throughout the package structure, preventing stress concentration at symmetric corners and eliminating delamination issues while maintaining manufacturing feasibility.
2Stability of the object's composition
If the semiconductor device is centered on the substrate, then the design is symmetrical and simple, but stress concentrates around die corners causing warpage
Solution Approach 1:
The semiconductor device is positioned offset from the center of the substrate, creating an asymmetric layout that eliminates corner stress concentration. The ring structure's cantilevered overhang portion further contributes to this asymmetric stress distribution, allowing thermal expansion forces to be distributed along the extended portion rather than concentrating at symmetric corners, thereby reducing warpage.
Solution Approach 2:
The ring structure extends into a third spatial dimension by cantilevering over the substrate edge. This dimensional extension provides additional space for stress distribution and allows the ring structure to act as a stress-relief element that compensates for CTE mismatch without requiring changes to the fundamental package layout.
3Stress or pressure
If a ring structure with cantilevered overhang is added, then stress is reduced by 25-35%, but the manufacturing process becomes more complex
Solution Approach 1:
The ring structure is integrated with the substrate during the wafer-level packaging process, combining multiple functions into a single manufacturing step. The ring structure serves both as a mechanical support element and as a stress-distribution feature, eliminating the need for separate post-processing steps to address stress concentration or add reinforcement structures.
Data Source
AI summary
A manufacturing method of a semiconductor package includes the following steps. A first semiconductor device is provided over a substrate, wherein the first semiconductor device is offset toward an edge of the substrate. A ring structure is attached to the substrate by a first adhesive layer, wherein the ring structure surrounds the first semiconductor device and comprises an overhang portion cantilevered over the edge of the substrate. A lid structure is attached to the ring structure by a second adhesive layer, wherein the lid structure covers the first semiconductor device and comprises an extending portion covering the overhang portion.