Semiconductor Package With Cavity Metal Plate For Heat Dissipation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor packaging technologies, such as fan-in packages, face challenges in accommodating a large number of I/O terminals and maintaining heat dissipation performance while allowing for compact design and efficient thermal properties.
Innovation Solution
A semiconductor package design featuring a cavity in a metal plate serving as an etching barrier, with insulated metal posts and a wiring layer, along with a redistribution layer, to enhance heat dissipation and design flexibility, allowing for a high-density pin configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fan-in packaging is used to accommodate more I/O terminals, then the number of pins increases, but the package size cannot be reduced and heat dissipation performance deteriorates
Solution Approach 1:
The patent transitions from fan-in packaging to fan-out packaging, changing the dimensional arrangement of I/O terminals from inward-facing to outward-facing. This dimensional change allows pins to be redistributed beyond the chip boundaries, increasing pin count while maintaining compact package size and improving heat dissipation through better thermal pathways.
Solution Approach 2:
The patent divides the package into distinct functional regions: a chip region containing the semiconductor chip, and a pad region containing the redistributed I/O terminals. This segmentation allows independent optimization of each region, enabling high pin density while maintaining thermal performance through separated heat generation and dissipation zones.
2Quantity of substance
If fan-out packaging is used to increase pin density, then the number of pins per unit area increases, but manufacturing complexity increases
Solution Approach 1:
The patent employs a substrate that serves multiple functions: it acts as the mounting platform for the semiconductor chip, provides the insulation layer for electrical isolation, forms the cavity structure for chip accommodation, and serves as the base for I/O terminal redistribution. This multi-functionality reduces the need for separate components, simplifying manufacturing despite the complex fan-out configuration.
3Volume of moving object
If compact package size is reduced to meet miniaturization demands, then device size decreases, but heat dissipation becomes more difficult
Solution Approach 1:
The patent applies different material properties and structural characteristics to different regions of the package. The chip region is optimized for electronic function with minimal size, while the pad region provides extended thermal pathways and I/O redistribution. The insulation layer with cavity structure provides localized thermal management, allowing compact overall size while maintaining heat dissipation performance through region-specific optimization.
Data Source
AI summary
A semiconductor package may include a frame including an insulation layer having a cavity formed in a lower surface of the insulation layer, a first post and a second post spaced apart from the cavity, and a metal plate disposed on an upper side of the cavity; a semiconductor chip having a first surface on which a connection pad is disposed and a second surface opposing the first surface; an encapsulant covering at least a portion of the semiconductor chip; and a connection structure disposed on the frame and the first surface of the semiconductor chip, and including one or more redistribution layers. The first post is electrically connected to the wiring layer of the frame and the redistribution layer of the connection structure, and the second post is spaced apart from the first post.