Semiconductor Package Cavity Design for Warpage Prevention
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Solution Overview
Problem
Semiconductor packages face warpage issues due to thermal expansion differences between devices and molds, require protection from physical impacts, and need to be miniaturized for thinner designs while accommodating electrodes on both surfaces.
Innovation Solution
A semiconductor package design featuring a molding member with a cavity larger than the device, an insulating member for impact protection, and a circuit layer with vias and connection pads, along with solder balls, where the molding member is cured before device mounting to prevent warpage and polished for reduced thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple heat treatments are performed to cure the mold and reflow solder, then the device is properly sealed and connected, but warpage occurs due to thermal expansion differences
Solution Approach 1:
The patent applies preliminary action by performing the curing process before mounting the device and conducting reflow operations. The mold is fully cured while the device is still in the mold cavity, eliminating subsequent thermal cycling that would cause warpage. This sequencing prevents the thermal expansion mismatch problem by completing all curing operations before the device is attached and subjected to reflow temperatures.
2Ease of manufacture
If the package structure is simplified, then manufacturing is easier, but protection from physical impact is reduced
Solution Approach 1:
The patent employs composite materials by combining the molding material with a cushioning layer made of foam or elastomer. This composite structure provides both mechanical protection against physical impacts and maintains ease of manufacture through a integrated molding process. The cushioning layer absorbs impact energy while the molding material provides structural integrity and electrical insulation.
3Length of moving object
If the package thickness is reduced for miniaturization, then the device size is decreased, but the cavity volume for mounting is reduced
Solution Approach 1:
The patent applies dimensionality change by transitioning from a traditional thick package structure to a thin-profile design where the cavity is formed within the plane of the molding member rather than extending through its thickness. The cavity forming pattern is integrated into the top surface of the thin molding member, allowing adequate cavity volume for device mounting while maintaining minimal overall package thickness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Prevents warpage due to thermal expansion, protects against physical impacts, and achieves miniaturization by allowing electrodes on both surfaces while reducing package thickness.
Implementation Method 1
a warpage phenomenon may be generated due to a difference in coefficient of thermal expansion between the device and the mold
Implementation Method 2
capable of protecting a device from physical impact applied from the outside
Data Source
AI summary
Disclosed herein are a semiconductor package and a method of manufacturing the same, the semiconductor package including: a molding member having a cavity formed therein; a device mounted in the cavity; an insulating member formed inside the cavity and on and/or beneath the molding member and the device; a circuit layer formed on the insulating member, and including vias and connection pads electrically connected with the device; a solder resist layer formed on the circuit layer, and having openings exposing upper portions of the connection pads; and solder balls formed in the openings.