Semiconductor Package Embedding Chips via Flip-Chip Bonding
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Solution Overview
Problem
Current semiconductor technologies face challenges in densely packing high-capacity semiconductor chips within limited spaces without increasing package thickness, particularly in establishing effective electrical connections between stacked chips.
Innovation Solution
A semiconductor package design that includes a substrate with multiple semiconductor chips flip-chip bonded and solder-jointed, utilizing bumps and solder balls for connections, eliminating the need for through-silicon vias (TSVs) to facilitate high-density chip embedding while maintaining electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-silicon vias (TSVs) are used to establish electrical connections between stacked chips, then electrical connectivity is achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent extracts and eliminates the TSV structure from the chip stacking system. Instead of forming through-silicon vias to achieve electrical connectivity, the invention uses alternative connection methods such as bump electrodes on chip edges or surface-mounted connection structures, thereby removing the complex TSV manufacturing process while maintaining electrical connectivity between stacked chips
Solution Approach 2:
The patent replaces expensive and complex TSV structures with simpler, cheaper connection elements such as bump electrodes or surface connection structures that can be manufactured using existing, more cost-effective processes, reducing overall manufacturing cost and complexity
2Quantity of substance
If multiple semiconductor chips are embedded in a single package, then chip capacity and functionality increase, but package area and layout complexity increase
Solution Approach 1:
The patent transitions from planar two-dimensional chip arrangement to three-dimensional vertical stacking. Multiple chips are stacked in the thickness direction (Z-axis) rather than being laid out side-by-side in the plane, enabling higher chip density without increasing package footprint area
Solution Approach 2:
The patent implements a nested structure where multiple chip components are vertically stacked and integrated within a single package body. The chips are arranged in layers similar to nested dolls, with each chip positioned above or below others, maximizing space utilization and enabling high-density integration
3Productivity
If chip thickness is reduced to increase chip count, then embedding density improves, but electrical connection reliability becomes more difficult to maintain
Solution Approach 1:
The patent applies different connection structures at different locations: edge-mounted bump electrodes for lateral connections and surface-mounted connection structures for vertical connections. This localized approach ensures reliable electrical connectivity despite reduced chip thickness, as each connection point is optimized for its specific position and function
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design allows for high-capacity, high-speed operation without the cost and processing complexities associated with TSVs, enabling efficient embedding of multiple chips, including memory and driving chips, while preventing the need for TSV formation, thus enhancing reliability and reducing costs.
Implementation Method 1
a first semiconductor chip flip-chip bonded to a first surface of the substrate. The semiconductor package may include second semiconductor chips respectively flip-chip bonded to portions of the first surface of the substrate
Implementation Method 2
The first semiconductor chip may comprise an SoC (system-on-chip) which has a substantially square planar shape... The first semiconductor chip further may comprise first connection members formed on the first bonding pads. The first connection members may comprise bumps.
Implementation Method 3
The semiconductor package may include a third semiconductor chip solder-jointed to the first surface of the substrate covering the first semiconductor chip and portions of the second semiconductor chips.
Data Source
AI summary
A semiconductor package may be provided. The semiconductor package may include a substrate. The semiconductor package may include a first semiconductor chip flip-chip bonded to a first surface of the substrate. The semiconductor package may include second semiconductor chips respectively flip-chip bonded to portions of the first surface of the substrate adjacent to both ends of the first semiconductor chip. The semiconductor package may include a third semiconductor chip solder-jointed to the first surface of the substrate covering the first semiconductor chip and portions of the second semiconductor chips.