Semiconductor Package 3D Conductive Layers IR Drop Reduction
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Solution Overview
Problem
Miniaturized semiconductor devices face issues with signal distortion and power supply voltage drop due to tiny metal wires transferring large electrical currents, leading to noise problems in ground and power connections.
Innovation Solution
A semiconductor package design featuring a substrate with multiple conductive layers and redistribution layers, along with adhesive layers to prevent short circuits, facilitates efficient signal transmission by exposing conductive layers for wire bonding and reducing electrical resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If tiny metal wires are used to transfer signals in miniaturized semiconductor devices, then device miniaturization is achieved, but signal distortion and power supply voltage drop (IR drop) occur due to large electrical currents
Solution Approach 1:
The patent transitions from planar 2D wiring to 3D vertical stacking with multiple conductive layers (first lower conductive layer, first upper conductive layer, second lower conductive layer, second upper conductive layer) connected via adhesive layers and wire bonds. This dimensional change provides additional current pathways and reduces IR drop while maintaining miniaturization.
Solution Approach 2:
The patent employs composite conductive structures combining multiple metal layers (aluminum, copper, or tungsten) with adhesive layers (polyimide or benzocyclobutene). This composite approach optimizes electrical conductivity while managing thermal and mechanical properties to reduce signal distortion and IR drop.
2Productivity
If device size is reduced, then integration density increases, but noise problems in ground and power connections worsen
Solution Approach 1:
The patent segments power and ground connections into multiple separate conductive layers and pathways. Power connections use dedicated layers (first upper conductive layer, second upper conductive layer) while ground connections use separate layers (first lower conductive layer, second lower conductive layer), preventing noise coupling and reducing electromagnetic interference.
Solution Approach 2:
Adhesive layers (polyimide or benzocyclobutene) serve as intermediary insulating barriers between conductive layers, preventing electrical short circuits while allowing thermal management and mechanical stress distribution, thereby reducing noise generation from poor connections.
3Reliability
If multiple conductive layers and adhesive layers are added to reduce IR drop, then electrical connection quality improves, but device complexity increases
Solution Approach 1:
The adhesive layers serve multiple functions simultaneously: electrical insulation between conductive layers, mechanical bonding support, thermal management, and stress distribution. This multi-functionality reduces the need for additional dedicated components, offsetting the complexity increase from multiple layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances signal transmission by reducing IR drop and noise issues, ensuring stable power and ground signals through lower and upper conductive layers with improved metal connection between the substrate and semiconductor chip.
Implementation Method 1
One of the adhesive layers is disposed between the first lower conductive layer and semiconductor chip. The adhesive layer insulates the first lower conductive layer from the semiconductor chip. Another adhesive layer is disposed between the first lower conductive layer and first upper conductive layer. The adhesive layer insulates the first lower conductive layer from the first upper conductive layer.
Data Source
AI summary
A semiconductor package includes a substrate and a semiconductor chip, a lower conductive layer and an upper conductive layer sequentially stacked on the substrate. The substrate includes first and second connection pads formed thereon. The semiconductor chip includes third and fourth connection pads formed thereon. The upper conductive layer is connected to the first and the third connection pads via a first and a second wiring, and the lower conductive layer is connected to the second and the fourth connection pads via a third and a fourth wiring.