Semiconductor Package Conductive Pattern Embedding
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Solution Overview
Problem
Current semiconductor packages face complexity and high manufacturing costs due to the use of electrically conductive wires for connecting semiconductor dies to substrates, and there is a need to maximize package integration while minimizing space on printed circuit boards.
Innovation Solution
The semiconductor package employs a conductive pattern partially embedded in a patterning layer for electrical connection, with wiring patterns embedded within the layer to connect dies to the substrate, reducing the need for external wires and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If electrically conductive wires are used to connect semiconductor dies to substrates, then reliable electrical connection is achieved, but manufacturing complexity and costs increase
Solution Approach 1:
The patent extracts the conductive connection function from separate wire bonds and integrates it directly into the substrate through embedded conductive patterns. This eliminates the need for external wire connections while maintaining electrical connectivity, thereby reducing manufacturing complexity without sacrificing connection reliability.
Solution Approach 2:
The patent merges the substrate and conductive interconnect structures into a single integrated component. The conductive patterns are formed directly on the substrate, combining the support function and electrical connection function into one unified structure, which simplifies the overall manufacturing process.
2Reliability
If electrically conductive wires are used for die-to-substrate connection, then electrical connectivity is established, but manufacturing costs increase
Solution Approach 1:
The patent removes the separate wire bonding step from the manufacturing process and replaces it with integrated conductive patterns formed during substrate fabrication. This extraction of the connection function from external wires reduces material costs and processing expenses.
Solution Approach 2:
The patent uses standard semiconductor fabrication processes to create conductive patterns that are inexpensive compared to precision wire bonding. The conductive traces are formed using conventional photolithography and deposition techniques already present in substrate manufacturing, eliminating the need for expensive wire bonding equipment and materials.
3Reliability
If conventional wire-based connection methods are used, then electrical connection is achieved, but space utilization on printed circuit boards decreases
Solution Approach 1:
The patent transitions from two-dimensional wire bonding to three-dimensional integrated circuit architecture. By embedding conductive patterns within the substrate and stacking semiconductor dies vertically, the design utilizes the third dimension (height) for interconnections, thereby reducing the horizontal footprint required on the printed circuit board.
Solution Approach 2:
The patent implements a nested structure where multiple semiconductor dies are stacked and interconnected through the substrate. The conductive patterns are embedded within the substrate layers, creating a compact nested arrangement that maximizes space utilization by vertical integration rather than horizontal expansion.
Data Source
AI summary
In accordance with the present invention, there is provided multiple embodiments of a semiconductor package including one or more semiconductor dies which are electrically connected to an underlying substrate through the use of a conductive pattern which is at least partially embedded in a patterning layer of the package. In a basic embodiment of the present invention, the semiconductor package comprises a substrate having a conductive pattern disposed thereon. Electrically connected to the conductive pattern of the substrate is at least one semiconductor die. The semiconductor die and the substrate are at least partially encapsulated by a patterning layer. Embedded in the patterning layer is a wiring pattern which electrically connects the semiconductor die to the conductive pattern. A portion of the wiring pattern is exposed in the patterning layer.