3D Stackable Semiconductor Package with Conductive Tunnels
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Solution Overview
Problem
Conventional semiconductor packages with fine pin pitches face challenges such as increased footprint, costly trimming tools, lead bending, and complex surface-mounting processes, which are not efficiently addressed by existing packaging materials and processes.
Innovation Solution
The development of a three-dimensional stackable semiconductor package using a sacrificial metal base strip with conducting tunnels filled by electroplating, allowing for higher density packaging without increasing the footprint, and enabling components to be stacked while maintaining electrical connectivity through wirebond pads and conductive tunnels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional plastic packages with leads along the perimeter are used to accommodate a large number of leads, then the number of external terminals increases, but the footprint of the package increases
Solution Approach 1:
The patent transitions from a two-dimensional perimeter lead arrangement to a three-dimensional area array configuration with conductive tunnels extending vertically through the encapsulant. This dimensional change allows multiple terminals to be accessed from both top and bottom surfaces, increasing terminal density without expanding the package footprint.
Solution Approach 2:
The patent embeds conductive tunnels within the encapsulant volume, nesting the electrical interconnection pathways inside the package body rather than routing them along the perimeter. This internal nesting of conductors allows for higher terminal density while maintaining a compact external footprint.
2Quantity of substance
If pin pitch is decreased to accommodate more pins without increasing footprint, then the number of terminals increases, but trimming costs increase and leads are prone to bending
Solution Approach 1:
The patent eliminates the need for fine-pitch perimeter leads by transitioning to area array terminals with conductive tunnels. The tunnel structure provides robust mechanical support for electrical connections, avoiding the bending and trimming issues associated with fine-pitch leads while accommodating a larger number of terminals.
Solution Approach 2:
The patent extracts the electrical interconnection function from the peripheral lead structure and relocates it to internal conductive tunnels. This extraction eliminates the problematic fine-pitch leads that require expensive trimming and are prone to bending, while maintaining high terminal density through the tunnel array configuration.
3Area of stationary object
If area array packages with specialized materials and processes are used, then footprint is reduced and terminal density increases, but manufacturing cost increases
Solution Approach 1:
The patent uses a polyimide substrate that serves multiple functions: it provides mechanical support, acts as an insulating layer, and supports the conductive pattern formation. This multi-functionality eliminates the need for separate specialized packaging components, reducing manufacturing complexity and cost while achieving compact area array packaging.
Solution Approach 2:
The patent employs standard electroplating processes to form conductive tunnels, using parameter changes in the plating process (such as copper deposition) to create the vertical conductive pathways. This approach uses conventional manufacturing techniques rather than specialized processes, reducing costs while achieving the required area array terminal density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for higher density integration of semiconductor devices on a printed circuit board without increasing the mounting area, reducing manufacturing costs and simplifying the surface-mounting process by enabling efficient stacking and electrical communication between components.
Implementation Method 1
Tunnels formed through an encapsulation volume surrounding the device and associated bond wires are filled with a metallic conductor by, for example, electroplating
Data Source
AI summary
An apparatus and methods for packaging semiconductor devices are disclosed. The apparatus is applicable to many types of contemporary packaging schemes that utilize a sacrificial metal base strip. Tunnels formed through an encapsulation area surrounding the device and associated bond wires are filled with a metallic conductor by, for example, electroplating, and extend bottom contact pads to an uppermost portion of the encapsulated area. The sacrificial metal base strip serves as a plating bus and is etch-removed after plating. The filled tunnels allow components to be stacked in a three-dimensional configuration.