Power Semiconductor Package Structure for CTE Separation Control
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Solution Overview
Problem
The difference in coefficient of thermal expansion between semiconductor elements and upper substrates in power semiconductor devices leads to separation during temperature cycles, compromising device integrity.
Innovation Solution
Incorporating through holes in the upper substrate and using a covering resin with a similar thermal expansion coefficient to the encapsulation resin, along with a wiring layer on the upper substrate, to stabilize the structure and prevent separation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the semiconductor element and upper substrate are directly bonded without through holes, then the structure is simple, but the upper substrate easily separates from the semiconductor element during temperature cycling due to CTE mismatch
Solution Approach 1:
The upper substrate is divided by forming through holes that extend from the upper surface to the lower surface, creating segmented regions that can independently accommodate thermal expansion. This segmentation allows each region to expand and contract separately during temperature cycling, reducing stress concentration and preventing separation at the bonding interface between the semiconductor element and upper substrate.
Solution Approach 2:
The through holes create a porous structure in the upper substrate that provides compliance to thermal expansion forces. The hollow spaces within and between the through holes allow the substrate to deform elastically during temperature cycles, absorbing the differential expansion between the semiconductor element and upper substrate without causing delamination.
2Reliability
If through holes are added to the upper substrate, then separation is prevented, but the device complexity increases
Solution Approach 1:
The through holes serve multiple functions simultaneously: they act as stress-relief features to prevent separation, provide pathways for wiring connections, and create compliance zones for thermal expansion. This multi-functionality reduces the need for additional separate components, thereby limiting the increase in overall device complexity while achieving the reliability improvement.
Solution Approach 2:
The covering resin acts as an intermediary material that fills the through holes and bonds the upper substrate to the lower substrate. This intermediary provides a compliant interface that accommodates differential thermal expansion while maintaining structural integrity, effectively mediating between the conflicting requirements of reliability and simplicity.
3Ease of manufacture
If the covering resin has different thermal expansion properties, then filling is easier, but thermal expansion-induced stress increases
Solution Approach 1:
The covering resin is specifically selected or formulated to have a coefficient of thermal expansion that closely matches both the upper substrate and the semiconductor element. This parameter matching minimizes differential thermal expansion during temperature cycling, reducing thermal stress at the interfaces while maintaining effective filling of the through holes and providing stable mechanical bonding.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively mitigates thermal expansion-induced separation, enhancing the reliability and durability of the semiconductor device by maintaining structural integrity under temperature variations.
Implementation Method 1
the difference in coefficient of thermal expansion between the semiconductor element and the upper substrate causes the upper substrate to easily separate from the semiconductor element
Implementation Method 2
an encapsulation resin disposed between the lower substrate and the upper substrate to encapsulate the semiconductor element
Data Source
AI summary
A semiconductor device includes a lower substrate, a semiconductor element mounted on an upper surface of the lower substrate, an upper substrate disposed on an upper surface of the semiconductor element, one or more through holes extending through the upper substrate in a thickness-wise direction, an encapsulation resin disposed between the lower substrate and the upper substrate and encapsulating the semiconductor element, a wiring layer disposed on an upper surface of the upper substrate, and a covering resin covering the upper surface of the upper substrate and filling the through holes.