Semiconductor Package CTE Tuning to Prevent Board Warpage
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Solution Overview
Problem
Semiconductor packages experience warpage due to differences in thermal expansion coefficients between the package and the circuit board, leading to mechanical and electrical defects.
Innovation Solution
A semiconductor package design with a structure comprising insulating layers stacked on the body portion, where the thickness and thermal expansion coefficients (CTEs) of these layers are adjusted to match a predetermined target CTE, typically 60% to 90% of the circuit board's CTE, using Equation (1) to ensure compatibility and minimize warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Weight of moving object
If the semiconductor package is miniaturized and thinned to meet lightweight and compact device requirements, then the weight and size of the package are reduced, but warpage occurs due to coefficient of thermal expansion (CTE) mismatch with the circuit board
Solution Approach 1:
The patent applies composite materials by stacking multiple insulating layers with different CTE values and thicknesses on the semiconductor chip. This creates a composite structure where the effective CTE of the entire package can be tuned to match the circuit board's CTE, thereby reducing warpage while maintaining the miniaturized and thinned package design.
Solution Approach 2:
The patent changes physical parameters by adjusting the CTE values and thicknesses of individual insulating layers in the stacked structure. By controlling these parameters, the effective CTE of the semiconductor package is optimized to match the circuit board, preventing warpage-induced mechanical and electrical defects while preserving the lightweight and compact form factor.
2Reliability
If multiple insulating layers are stacked on the semiconductor chip to adjust the effective CTE, then the CTE mismatch with the circuit board is reduced, but the structural complexity of the package increases
Solution Approach 1:
The patent segments the insulating structure into multiple distinct layers, each with specific CTE values and thicknesses. This segmentation allows independent optimization of each layer's properties to achieve the desired effective CTE for the entire package, while maintaining a systematic and manufacturable structure through standardized layering processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design ensures the semiconductor package and module have similar CTEs to the circuit board, preventing warpage and associated damage, thereby enhancing reliability.
Implementation Method 1
there is a problem that warpage occurs due to a difference in a coefficient of thermal expansion between the semiconductor package and a circuit board on which the semiconductor package is mounted
Data Source
AI summary
A semiconductor package, as a semiconductor package mounted on a circuit board, includes including: a body portion including a semiconductor chip, and a first surface and a second surface opposite to each other; and a structure including n insulating layers stacked on at least one of the first surface and the second surface of the body portion, wherein the semiconductor package has a predetermined target coefficient of thermal expansion (CTE), and the n insulating layers and the body portion have a thickness and a CTE satisfying a condition that an effective CTE of the semiconductor package becomes equal to the predetermined target CTE.