Semiconductor Package Dimples for Shear Stress Reduction
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Solution Overview
Problem
High power semiconductor packages experience reduced thermal and mechanical reliability due to shear stress caused by differences in thermal expansion coefficients between the insulation substrate, interconnection patterns, and encapsulation materials, leading to delamination and shortened lifespan.
Innovation Solution
Incorporating first and second dimples in the interconnection patterns and base metal layer to reduce shear stress, with the first dimples on the insulation substrate's surface and second dimples on the base metal layer's edge, which helps in reducing thermal expansion-induced deformation and improving moisture resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional wire bonding and epoxy molding are used, then electrical connection is achieved, but shear stress causes delamination and reduces reliability
Solution Approach 1:
The patent introduces dimples (curved凹陷 structures) in the interconnection patterns and base metal layer to reduce stress concentration. These dimples transform the flat rigid structure into a curved one that can better accommodate thermal expansion differences, thereby reducing shear stress and preventing delamination while maintaining electrical connection reliability
Solution Approach 2:
The patent modifies the physical parameters of the interconnection structure by creating dimples with specific depths (10%-100% of interconnection pattern thickness) and diameters (0.1mm to 3mm). These parameter changes allow the structure to better absorb thermal stress without compromising electrical conductivity or mechanical strength
2Reliability
If thermal expansion differences are not addressed, then manufacturing is simple, but shear stress concentrates and causes delamination
Solution Approach 1:
The dimples introduce curved geometry into the otherwise flat interconnection patterns. This curvature allows the structure to flex and accommodate thermal expansion differences between materials, reducing stress concentration at edges while maintaining electrical connectivity and requiring only moderate additional manufacturing steps
3Object-affected harmful factors
If edge density of dimples is increased, then moisture permeation is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent applies different dimple densities to different regions: higher density at edges where moisture permeation is most problematic, and lower density in center areas. This localized quality approach effectively reduces moisture ingress at critical interfaces while minimizing overall manufacturing complexity and material usage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dimples significantly reduce shear stress by about 72% and enhance moisture resistance, maintaining the electrical and mechanical characteristics of the semiconductor package even after repeated thermal cycles.
Implementation Method 1
shear stress which may result from a difference in thermal expansion coefficients of an insulating substrate and a metallic interconnection pattern
Implementation Method 2
The first dimples may be formed in an edge of the interconnection patterns so as to reduce shear stress concentrated at the edge of the interconnection patterns
Data Source
AI summary
Provided is a high power semiconductor package including: an insulation substrate having first and second surfaces opposite to each other; an interconnection patterns formed on the first surface of the insulation substrate, the interconnection patterns including a plurality of first dimples; a power control semiconductor chip mounted on the first surface of the insulation substrate, the power control semiconductor chip electrically connected with the interconnection patterns; and an encapsulation member encapsulating the insulation substrate, the interconnection patterns, and the power control semiconductor chip and exposing at least a portion of the second surface of the insulation substrate.