Semiconductor Package Direct Wire Bonding Signal Integrity
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Solution Overview
Problem
Conventional system-in-package (SiP) packaging experiences signal integrity issues such as high insertion loss, return loss, and channel resonance due to impedance discontinuity and high crosstalk in the signal connection path formed by wire bonding techniques, which affects high-speed signal communication between semiconductor dies.
Innovation Solution
A semiconductor package design featuring a carrier substrate with chips mounted side-by-side, using direct bonding wires to connect high-speed signal pads on one chip to data pads on another chip, bypassing the gold fingers and traces in the substrate, and incorporating a redistribution layer to fan out signal pads, along with an encapsulant and solder balls for attachment to a PCB.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding technique is used to connect dies to package substrate, then electrical connection is established, but signal integrity deteriorates due to impedance discontinuity and crosstalk
Solution Approach 1:
The patent extracts the high-speed signal connection path from the package substrate's gold fingers and traces, creating a dedicated direct bonding wire connection between chips that bypasses the substrate's signal path. This separation removes the source of impedance discontinuity and crosstalk from the critical high-speed signal path.
Solution Approach 2:
The patent segments the connection paths by creating separate dedicated bonding wire connections for high-speed signals, command/address signals, and power/ground signals. This segmentation isolates high-speed data signals from other signal types, reducing crosstalk and improving signal integrity.
2Reliability
If direct bonding wires are used to connect high-speed signal pads, then signal integrity improves, but manufacturing complexity increases
Solution Approach 1:
The patent positions the high-speed signal pads and DQ pads in adjacent locations on the chips before wire bonding, and pre-configures the bonding wire paths. This preliminary arrangement simplifies the wire bonding process by reducing the complexity of routing and minimizing the number of bonding steps required.
Solution Approach 2:
The patent introduces an adhesion layer as an intermediary between the chips and package substrate, and uses bonding wires as intermediaries to create direct electrical connections. These intermediaries facilitate the complex connections by providing standardized interfaces and simplifying the bonding process.
3Length of stationary object
If signal pads are directly connected via bonding wires, then connection length is reduced, but signal distortion increases without proper signal routing
Solution Approach 1:
The patent applies different connection strategies to different signal types based on their specific requirements. High-speed signal pads are directly connected with bonding wires for minimal length, while command/address pads use gold finger connections, and power/ground pads use dedicated bonding wires. This localized optimization ensures each signal type has the appropriate connection quality.
Solution Approach 2:
The patent redistributes signal pads in the lateral dimension on the chip surface, placing high-speed signal pads adjacent to DQ pads to enable direct bonding wire connections. This spatial rearrangement in two dimensions allows for shorter three-dimensional connection paths while maintaining signal integrity.
Data Source
AI summary
A semiconductor package includes a carrier substrate including opposite first surface and second surface; a first chip and a second chip mounted on the first surface of the carrier substrate in a side-by-side manner, wherein the first chip has a plurality of high-speed signal pads disposed along its first side adjacent to the second chip, and the second chip has a plurality of data (DQ) pads along its second side adjacent to the first chip; and a plurality of first bonding wires, directly connecting the plurality of high-speed signal pads to the plurality of data (DQ) pads.