Semiconductor Package Layout With Embedded Passives and Low Warpage
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Solution Overview
Problem
The semiconductor industry faces challenges in miniaturizing integrated circuits while maintaining high functional density and electrical performance, particularly in reducing warping and increasing structural support in small packages, which is not adequately addressed by existing packaging technologies.
Innovation Solution
The proposed solution involves forming a semiconductor device package with a redistribution structure and integrated passive devices within a molding material, reducing the distance between the semiconductor device and the passive devices, and using multiple molding layers for structural support, which improves electrical performance and reduces warping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the package size is reduced for miniaturization, then the portability and application flexibility are improved, but the structural support and warping resistance are worsened
Solution Approach 1:
The patent employs a composite package structure combining organic substrate material with an inorganic warping prevention layer (such as metal or ceramic layers). This composite approach allows the package to maintain small volume while the inorganic layer provides enhanced structural support and warping resistance that pure organic materials cannot achieve alone.
Solution Approach 2:
The package structure is segmented into distinct functional layers: the organic substrate layer for electrical interconnection and the separate inorganic warping prevention layer for structural support. This segmentation allows each layer to optimize its specific function without compromising the other, enabling miniaturization while maintaining strength.
2Reliability
If the distance between semiconductor device and passive devices is reduced, then the electrical performance and high-frequency operation are improved, but the routing complexity and manufacturing difficulty are worsened
Solution Approach 1:
The patent transitions from planar routing to three-dimensional vertical routing by stacking passive devices directly above or adjacent to the semiconductor device in the vertical dimension. This dimensional change reduces the lateral routing distance and complexity while maintaining electrical performance, as signals travel vertically through vias rather than laterally through complex trace networks.
Solution Approach 2:
The package structure nests passive devices within the vertical space above the semiconductor device, utilizing the third dimension for component placement. This nesting approach minimizes the overall footprint and routing complexity by organizing components in a compact vertical hierarchy rather than spreading them out horizontally.
3Productivity
If more input/output pads are integrated for high functionality, then the functional density is improved, but the pitch between contact pads increases making miniaturization difficult
Solution Approach 1:
The patent utilizes vertical stacking to increase functional density without increasing the lateral footprint. Multiple I/O pads and passive devices are arranged in vertical layers, allowing high functionality to be achieved within a small planar area by exploiting the third dimension for component placement and interconnection.
Solution Approach 2:
The I/O interface is segmented across multiple vertical layers, with different functional pads distributed throughout the stack. This segmentation allows each layer to be optimized independently and enables high functional density by utilizing the vertical space for additional I/O functionality without increasing the contact pad pitch on any single layer.
Data Source
AI summary
A package includes a first layer of molding material, a first metallization layer on the first layer of molding material, a second layer of molding material on the first metallization layer and the first layer of molding material, a second metallization layer on the second layer of molding material, through vias within the second layer of molding material, the through vias extending from the first metallization layer to the second metallization layer, integrated passive devices within the second layer of molding material, a redistribution structure electrically on the second metallization layer and the second layer of molding material, the redistribution structure connected to the through vias and the integrated passive devices, and at least one semiconductor device on the redistribution structure, the at least one semiconductor device connected to the redistribution structure.