Semiconductor Package Insulating Encapsulant Stress Management

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Solution Overview

Problem

The reliability of underfill protection in semiconductor packages is a critical issue due to stress concentrations at interfaces, which can lead to cracking or delamination, and existing methods do not effectively manage these stresses.

Innovation Solution

A semiconductor package structure is designed with a specific configuration of insulating encapsulant and interposer structure, featuring a protruding second portion and beveled surfaces, which reduces stress at interfaces by optimizing the encapsulant's height and width ratios and the interposer's surface profiles, thereby enhancing adhesion and preventing underfill bleeding or creeping.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the insulating encapsulant and interposer structure use conventional flat interfaces, then the manufacturing process is simple, but stress concentrations occur at interfaces leading to cracking or delamination

Engineering Contradiction:
Improveinterface adhesion reliabilityVSAvoidencapsulant and interposer structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies asymmetry by introducing beveled surfaces at the interfaces between the insulating encapsulant and interposer structure, replacing conventional flat symmetric interfaces. The beveled surfaces create asymmetric geometry that distributes stress more evenly across the interface, preventing stress concentration points that would lead to cracking or delamination. This asymmetric design enhances interface adhesion reliability while maintaining manufacturing feasibility.

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The patent applies curvature principles through the beveled surface geometry, which creates gradual transitions rather than abrupt flat interfaces. The angled surfaces provide a tapered transition zone that reduces stress concentration by distributing mechanical loads more uniformly across the interface area, thereby improving reliability without significantly increasing device complexity.

Inventive Principle:
Principle #14Spheroidality (Curvature)

2Reliability

If the insulating encapsulant has uniform height and width, then the structure is simple to manufacture, but stress is not effectively managed at interfaces

Engineering Contradiction:
Improvestress management capabilityVSAvoidencapsulant dimension control precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies local quality by creating non-uniform dimensions in the insulating encapsulant, specifically with varying height and width across different regions. The encapsulant features different dimensional characteristics at different locations to optimize stress distribution at critical interfaces. This localized dimensional variation improves stress management capability while requiring enhanced manufacturing precision to control the specific dimension tolerances.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11164824B2Package structure and method of fabricating the same
Publication Date: 2021.11.02 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11164824B2 patent drawing
  • US11164824B2 patent drawing
  • US11164824B2 patent drawing

AI summary

A package structure includes a circuit substrate and a semiconductor package. The semiconductor package is disposed on the circuit substrate, and includes a plurality of semiconductor dies, an insulating encapsulant and a connection structure. The insulating encapsulant comprises a first portion and a second portion protruding from the first portion, the first portion is encapsulating the plurality of semiconductor dies and has a planar first surface, and the second portion has a planar second surface located at a different level than the planar first surface. The connection structure is located over the first portion of the insulating encapsulant on the planar first surface, and located on the plurality of semiconductor dies, wherein the connection structure is electrically connected to the plurality of semiconductor dies and the circuit substrate.