Semiconductor Package Layout With Exposed Dies for Heat Dissipation

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Solution Overview

Problem

Semiconductor devices integrating multiple modules face challenges with heat dissipation and process complexity.

Innovation Solution

The integration of an interconnection module elevates the second semiconductor module, allowing both top surfaces to be at the same plane and exposed by a molding material for effective heat dissipation, and simplifies the manufacturing process by forming the RDL module directly on pre-formed semiconductor modules without solder joints, reducing the need for multiple carriers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple semiconductor modules are integrated in a stacked configuration, then device functionality and integration density are improved, but heat dissipation becomes more difficult and process complexity increases

Engineering Contradiction:
Improvedevice functionalityVSAvoidprocess complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The method performs preliminary actions by forming the RDL module and interconnection module structures on the carrier before mounting the semiconductor modules. This allows the complex interconnection structures to be prepared in advance, simplifying the subsequent module integration process and reducing overall process complexity

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The device is segmented into distinct functional modules (semiconductor modules, RDL module, interconnection module) that can be independently fabricated and then integrated. This modular approach allows each module to be optimized separately while maintaining overall system functionality

Inventive Principle:
Principle #1Segmentation

2Reliability

If multiple semiconductor modules are integrated with solder joints, then electrical connection is achieved, but manufacturing complexity and cost increase

Engineering Contradiction:
Improveelectrical connectionVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The method merges the RDL module and interconnection module functions into a single integrated structure formed on the carrier. This consolidation eliminates the need for separate solder joint processes between modules, reducing manufacturing complexity while maintaining reliable electrical connections through the integrated conductive pathways

Inventive Principle:
Principle #5Merging (Combining)

3Adaptability or versatility

If semiconductor modules are mounted at different heights, then integration flexibility is improved, but heat dissipation efficiency deteriorates

Engineering Contradiction:
Improveintegration flexibilityVSAvoidheat dissipation efficiency
Core Design Contradiction:
Adaptability or versatilityVSTemperature

Solution Approach 1:

The patent transitions from vertical stacking (single dimension) to a planar arrangement where multiple semiconductor modules are mounted at the same height on the carrier (two-dimensional layout). This dimensional change allows all module top surfaces to be exposed for heat dissipation while maintaining integration flexibility through the carrier substrate

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12593732B2Semiconductor device and manufacturing method thereof
Publication Date: 2026.03.31 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12593732B2 patent drawing
  • US12593732B2 patent drawing
  • US12593732B2 patent drawing

AI summary

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a redistribution layer (RDL) module, a first semiconductor module, an interconnection module, a second semiconductor module and a molding material. The first semiconductor module is disposed on the RDL module. The interconnection module is disposed on the RDL module. The second semiconductor module is disposed on the interconnection module. The molding material covers the RDL module and surrounds the first semiconductor module and the second semiconductor module. A top surface of the first semiconductor module and a top surface of the second semiconductor module are exposed by the molding material.