Semiconductor Package Insulating Layer Openings for Encapsulant Filling
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Solution Overview
Problem
Semiconductor packages face challenges in achieving high production yields due to non-filling and swelling phenomena of encapsulants, which affect adhesion and flowability, leading to voids and reduced performance.
Innovation Solution
The semiconductor package design includes a package substrate with a first insulating layer, wiring layers, and a second insulating layer with openings that expose the first insulating layer between semiconductor chips, allowing the encapsulant to fill these openings and increase adhesion, thereby preventing non-filling and swelling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the encapsulant is used to fill spaces between support members and semiconductor chips, then adhesion and protection are improved, but non-filling and swelling phenomena occur reducing production yield
Solution Approach 1:
The second insulating layer is divided into multiple regions with different properties: a first region covering wiring layers for electrical isolation, and a second region without wiring layers that is removed to form openings. This segmentation allows the encapsulant to selectively fill only the second region, preventing non-filling and swelling while maintaining adhesion in critical areas.
Solution Approach 2:
Different regions of the insulating layer are designed with different properties: the first region maintains coverage for adhesion and electrical isolation, while the second region is removed to create openings that facilitate complete encapsulant filling. This local quality differentiation resolves the contradiction between maintaining adhesion and preventing filling defects.
2Reliability
If the second insulating layer covers the wiring layer completely, then electrical isolation is improved, but encapsulant flowability and filling are reduced
Solution Approach 1:
The second insulating layer is segmented into a first region that covers wiring layers for electrical isolation and a second region that is removed to form openings. This segmentation maintains electrical isolation where needed while enabling encapsulant flow and filling in the opened regions.
Solution Approach 2:
The openings are formed in the second insulating layer before the encapsulant is applied. This preliminary action creates pathways that facilitate complete encapsulant filling and prevents non-filling defects, while the remaining first region maintains electrical isolation.
3Ease of manufacture
If openings are formed in the second insulating layer, then encapsulant filling is improved, but adhesion strength may be reduced
Solution Approach 1:
The insulating layer is designed with local quality differentiation: the first region maintains full coverage for adhesion strength, while only the second region is removed to form openings. This ensures that adhesion is preserved in critical areas while enabling complete encapsulant filling in non-critical areas.
Solution Approach 2:
The second insulating layer is segmented into adhesion-critical first regions that are retained and non-critical second regions that are removed. This segmentation maintains overall adhesion strength while facilitating encapsulant filling through the removed portions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the adhesion and flowability of the encapsulant, preventing voids and swelling, resulting in increased production yields and improved semiconductor package performance.
Implementation Method 1
the opening is filled with the encapsulant
Implementation Method 2
enhances the adhesion and flowability of the encapsulant
Data Source
AI summary
A semiconductor package includes a package substrate having a first insulating layer, a wiring layer disposed on the first insulating layer, and a second insulating layer disposed on the first insulating layer and covering at least a portion of the wiring layer, a pair of support members disposed to face each other on the second insulating layer of the package substrate, and a pair of semiconductor chips disposed between the pair of support members and electrically connected to the wiring layer, wherein the second insulating layer has an opening surrounding at least a portion of each of the pair of semiconductor chips.