Semiconductor Package Groove Insulating Layer Warpage

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Solution Overview

Problem

Conventional semiconductor packages experience warpage due to stress release when the supporting substrate is removed during manufacturing, caused by mismatched thermal expansion coefficients between the semiconductor chip and the insulating layers.

Innovation Solution

The semiconductor package incorporates a groove structure in the outermost interlayer insulating layer and a buried resin layer with a thermal expansion coefficient matching that of the semiconductor chip, reducing stress and warpage by segmenting the insulating layers and aligning the thermal expansion coefficients.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If the supporting substrate is removed after mounting the semiconductor chip and forming the wiring structure, then the semiconductor package can be completed and detached for use, but warpage occurs due to stress release from the supporting substrate

Engineering Contradiction:

Improvecompletion of semiconductor packageVSAvoidwarpage of semiconductor package

Core Design Contradiction:

Ease of manufactureVSShape

Solution Approach 1:

The patent divides the outermost interlayer insulating layer into multiple segments by forming grooves that extend in the thickness direction. This segmentation allows each segment to independently adjust and release stress when the supporting substrate is removed, preventing overall warpage of the semiconductor package while maintaining the ability to complete the package manufacturing process

Inventive Principle:

Principle #1Segmentation

2Reliability

If insulating layers are formed to cover the semiconductor chip and form wiring structures, then electrical connection and insulation are achieved, but thermal expansion mismatch causes stress and warpage

Engineering Contradiction:

Improveelectrical connection and insulationVSAvoidstress from thermal expansion mismatch

Core Design Contradiction:

ReliabilityVSStress or pressure

Solution Approach 1:

The grooves divide the outermost interlayer insulating layer into multiple independent segments, allowing each segment to expand and contract independently in response to thermal changes. This reduces the cumulative stress from thermal expansion mismatch between the semiconductor chip and insulating layers, preventing warpage while maintaining electrical connection and insulation reliability

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces grooves at specific locations in the outermost interlayer insulating layer, creating local variations in the structure. These localized grooves allow stress relief at critical points where thermal expansion mismatch occurs, while maintaining the overall integrity and electrical functionality of the insulating layers

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively reduces warpage by alleviating stress and maintaining a flat shape of the semiconductor package, ensuring reliable stacking and assembly.

Implementation Method 1

A groove formed in the outermost interlayer insulating layer passes through the outermost interlayer insulating layer in a thickness direction

Methodology Applied

Scientific EffectStress distribution:

Implementation Method 2

a buried resin layer with a thermal expansion coefficient matching that of the semiconductor chip, reducing stress and warpage by segmenting the insulating layers and aligning the thermal expansion coefficients

Methodology Applied

Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentUS8823187B2Semiconductor package, semiconductor package manufacturing method and semiconductor device

Publication Date: 2014.09.02 SHINKO ELECTRIC IND CO LTD

AI summary

A semiconductor package includes a semiconductor chip, a first insulating layer formed to cover the semiconductor chip, a wiring structure formed on the first insulating layer. The wiring structure has an alternately layered configuration including wiring layers electrically connected to the semiconductor chip and interlayer insulating layers each located between one of the wiring layers and another. The interlayer insulating layers include an outermost interlayer insulating layer located farthest from a surface of the first insulating layer. A groove formed in the outermost interlayer insulating layer passes through the outermost interlayer insulating layer in a thickness direction.