Semiconductor Package Heat Dissipating Conductors
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Solution Overview
Problem
The challenge in semiconductor packaging is to efficiently dissipate heat generated by small semiconductor chips while maintaining a compact size, as existing technologies face difficulties in balancing heat dissipation efficiency with manufacturing complexity and size constraints.
Innovation Solution
A semiconductor package design featuring a core layer with a device accommodating portion, a buildup layer with heat dissipating conductors that expose externally through an insulating protective layer, and a lattice arrangement of heat dissipating pads with a specific diameter-to-pitch ratio, optimized for efficient heat dissipation and manufacturing simplicity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If heat dissipating conductors are added to the buildup layer, then heat dissipation efficiency is improved, but device complexity increases
Solution Approach 1:
The heat dissipating conductors are integrated into the existing buildup layer structure, allowing the same structural elements to serve both as insulating layers and as heat dissipation pathways. The buildup layer simultaneously provides electrical insulation and thermal management functions, eliminating the need for separate dedicated heat dissipation structures.
Solution Approach 2:
The buildup layer materials are selected to inherently provide both insulation and heat dissipation properties. The insulating protective layer and buildup layer materials themselves serve as heat dissipation conduits, utilizing their own thermal conductivity properties rather than requiring additional specialized components.
2Temperature
If the total area of heat dissipating pads is increased, then heat dissipation efficiency is improved, but the area ratio exceeds 35.5% which may affect device layout
Solution Approach 1:
The patent optimizes the heat dissipating pad dimensions and spacing parameters to achieve effective heat dissipation within the constrained area ratio. By adjusting the diameter and separation distance parameters, the design achieves optimal thermal performance without exceeding the 35.5% area threshold.
Solution Approach 2:
Instead of increasing heat dissipation capacity solely through larger pad areas, the patent utilizes the vertical dimension by stacking multiple heat dissipating conductors in the buildup layer. This allows heat dissipation to occur through multiple layers at different heights, effectively increasing the heat dissipation surface area without proportionally increasing the planar footprint.
3Temperature
If heat dissipating conductors are disposed in a lattice form with specific D/P ratio, then heat dissipation efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The lattice pattern of heat dissipating conductors is pre-designed and pre-positioned within the buildup layer during the packaging process. The conductors are placed in predetermined locations with predetermined spacing before final encapsulation, allowing for controlled positioning that simplifies subsequent manufacturing steps while ensuring optimal heat dissipation geometry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces the temperature of the semiconductor package by optimizing the size and spacing of heat dissipating pads, achieving efficient heat emission while maintaining a compact size and simplifying manufacturing processes.
Implementation Method 1
heat dissipating conductors disposed in the buildup layer to externally emit heat generated by the electronic device
Data Source
AI summary
A semiconductor package includes a substrate portion including a core layer having a device accommodating portion formed therein, and a buildup layer stacked on each of opposing sides of the core layer; an electronic device disposed in the device accommodating portion; and heat dissipating conductors disposed in the buildup layer to externally emit heat generated by the electronic device.