Semiconductor Package Insulation Protrusions for CTE Management
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor packages face challenges in managing thermal expansion, particularly as devices become smaller and more complex, leading to issues with coefficient of thermal expansion (CTE) that affect performance and reliability.
Innovation Solution
A semiconductor package design featuring a package substrate with a circuit pattern, insulation layers, and protrusions that adjust the CTE by varying the mass ratio of conductive material, specifically reducing conductive material in non-essential regions to enhance thermal management without compromising signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive material is increased in the package substrate, then electrical conductivity is improved, but coefficient of thermal expansion increases
Solution Approach 1:
The patent applies local quality by creating different protrusion structures in different regions of the package substrate. First protrusions with mesh structures are positioned under the chip mounting region to provide localized CTE adjustment, while second protrusions with larger cross-sectional areas are positioned in non-mounting regions. This spatial differentiation allows the substrate to maintain appropriate electrical conductivity in chip regions while reducing overall CTE through strategically placed protrusions in non-essential areas.
Solution Approach 2:
The patent employs parameter changes by varying the physical characteristics of protrusions to control CTE. The mesh structure of first protrusions provides a specific surface area-to-volume ratio for CTE management in chip regions, while the larger cross-sectional area of second protrusions in non-mounting regions provides different mechanical and thermal properties. This parameter variation enables fine-tuning of the overall CTE while preserving electrical functionality.
2Temperature
If conductive material is reduced in non-essential regions, then coefficient of thermal expansion is reduced, but signal integrity may be compromised
Solution Approach 1:
The patent ensures signal integrity is maintained by concentrating conductive material and protrusion structures in specific locations. First protrusions with mesh structures are positioned directly under the chip mounting region where signal integrity is critical, while second protrusions are placed in non-mounting regions where they provide CTE adjustment without interfering with signal paths. This localized quality distribution ensures that CTE reduction measures do not compromise electrical performance in essential areas.
Solution Approach 2:
The protrusions serve as intermediary structures that mediate between the requirement for low CTE and the need for signal integrity. By positioning protrusions in non-mounting regions and using mesh structures that provide both mechanical support and thermal management, the patent creates intermediate zones that adjust CTE while leaving critical signal transmission paths unaffected. The protrusions act as mediators that reconcile the conflicting requirements of thermal management and electrical performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces the effective coefficient of thermal expansion (CTE) by about 2.7% to 8% across temperature intervals, maintaining electrical characteristics and signal integrity while reducing conductive material usage.
Implementation Method 1
a first insulation layer includes first protrusions which protrude from a bottom surface of the first insulation layer, penetrate through at least a portion of the circuit pattern, and have a mesh structure
Implementation Method 2
A second protrusion protrudes from the bottom surface of the first insulation layer and penetrates at least a portion of the circuit pattern. The second protrusion is spaced apart from the semiconductor chip in the horizontal direction. The second protrusion has a width in the horizontal direction wider than that of each of the first protrusions
Data Source
AI summary
A semiconductor package includes a circuit pattern extending in a horizontal direction. The circuit pattern is conductive. A first insulation layer is disposed on the circuit pattern. A semiconductor chip is disposed on the first insulation layer. The first insulation layer includes first protrusions which protrude from a bottom surface of the first insulation layer, penetrate through at least a portion of the circuit pattern, and have a mesh structure. A second protrusion protrudes from the bottom surface of the first insulation layer and penetrates at least a portion of the circuit pattern. The second protrusion is spaced apart from the semiconductor chip in the horizontal direction. The second protrusion has a width in the horizontal direction wider than that of each of the first protrusions.