Semiconductor Package Land Asymmetry for Signal Synchronization
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Solution Overview
Problem
In stacked semiconductor packages with a PoP structure, variations in wiring length cause differences in transmission line characteristics, leading to signal waveform variations and synchronization issues between semiconductor chips.
Innovation Solution
The solution involves designing the stacked semiconductor package with first and second lands of different surface areas and corresponding wirings of varying lengths, where the second land has a larger surface area and wiring length than the first, to adjust parasitic capacitance and inductance, thereby reducing differences in transmission line characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple transmission lines are used for communication between semiconductor chips, then communication functionality is improved, but synchronization of signals becomes difficult to ensure due to variations in wiring length and transmission line characteristics
Solution Approach 1:
The patent applies local quality by making each land have a different surface area tailored to its specific wiring length. Lands connected to longer wirings have larger surface areas to provide additional parasitic capacitance, while lands connected to shorter wirings have smaller surface areas. This localized customization of land dimensions compensates for the varying transmission line characteristics caused by different wiring lengths, ensuring uniform signal transmission across all communication lines.
2Adaptability or versatility
If wiring length is increased to connect distant lands, then connection flexibility is improved, but transmission line characteristics vary due to difference in parasitic inductance
Solution Approach 1:
The patent employs parameter changes by systematically varying the surface area parameter of lands based on their connection distance from the semiconductor element. The land surface area is adjusted as a compensating parameter to offset changes in wiring length. This parameter adjustment modifies the parasitic capacitance of each land-wiring combination, thereby standardizing the overall transmission line characteristics despite variations in wiring geometry.
3Reliability
If land surface area is increased to compensate for wiring length variation, then transmission line characteristics are improved, but manufacturing complexity increases
Solution Approach 1:
The patent implements asymmetry by deliberately designing lands with non-uniform surface areas instead of using identical standardized lands for all connections. Each land's dimensions are asymmetrically adjusted according to its specific position and wiring length requirements. This asymmetric design, while appearing complex, actually simplifies the overall system by eliminating the need for additional compensation circuits or complex routing adjustments, as the compensation is built directly into the land geometry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures signal synchronization and enhances high-speed transmission characteristics by minimizing differences in transmission line characteristics, allowing for both downsizing and thinning of the semiconductor package while maintaining effective communication.
Implementation Method 1
a parasitic capacitance generated at the second land is larger than a parasitic capacitance generated at the first land, and thus, difference in transmission line characteristics due to difference in wiring length can be reduced
Data Source
AI summary
A semiconductor package includes a printed wiring board and a semiconductor chip that has a first signal terminal and a second signal terminal and is mounted on the printed wiring board. The printed wiring board has a first land and a second land for solder joining, which are formed on a surface layer thereof. Further, the printed wiring board has a first wiring for electrically connecting the first signal terminal of the semiconductor chip and the first land, and a second wiring for electrically connecting the second signal terminal of the semiconductor chip and the second land. The second wiring is formed so that the wiring length thereof is larger than that of the first wiring. The second land is formed so that the surface area thereof is larger than that of the first land. This reduces difference in transmission line characteristics due to the difference in wiring length.