Semiconductor Package Lead Frame Design for Heat Dissipation
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Solution Overview
Problem
Semiconductor package devices face challenges with heat dissipation and stray inductance issues, leading to increased switching losses due to the generation of stray inductance at wires and lead frames, which affects the performance of semiconductor chips.
Innovation Solution
A semiconductor package device design featuring a lead frame with slanted and bent lead frame leads attached to a direct bonded copper substrate, along with a solder resist layer and heat sink, which enhances heat dissipation and reduces internal impedance by eliminating the need for conventional wire bonding and optimizing the angle of the slanted leads based on the chip height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional wire bonding is used to connect the semiconductor chip to the lead frame, then electrical connection is achieved, but stray inductance is generated which increases switching loss
Solution Approach 1:
The patent extracts and eliminates the wire bonding process from the semiconductor package structure. Instead of using separate wires to connect the chip to the lead frame, the lead frame leads are directly attached to the chip electrodes, removing the source of stray inductance and simplifying the overall structure.
Solution Approach 2:
The patent merges the lead frame leads with the chip electrodes by directly attaching the leads to the chip. This integration eliminates the separate wire bonding step and reduces the number of electrical connection interfaces, thereby reducing stray inductance and switching loss.
2Temperature
If heat is discharged downward from the lead frame, then some heat dissipation is achieved, but residual heat discharged upward through the EMC is insufficient
Solution Approach 1:
The patent segments the heat dissipation paths into distinct upward and downward directions. The lead frame is designed with specific lead configurations that facilitate downward heat discharge, while the substrate and EMC are engineered to provide an efficient upward heat discharge path, creating a dual-path heat dissipation system.
Solution Approach 2:
The substrate serves multiple functions: it provides electrical connection between the chip and external circuits, mechanical support for the chip, and a heat dissipation pathway. The EMC also serves dual purposes as both encapsulation material and heat dissipation medium for upward heat discharge.
3Reliability
If the lead frame leads are made highly conductive, then electrical connection is improved, but internal impedance increases which affects performance
Solution Approach 1:
The patent employs slanted and bent configurations in the lead frame leads instead of straight rigid connections. The curved and angled paths of the leads reduce impedance by optimizing the current flow geometry and minimizing sharp corners and discontinuities in the electrical path.
Solution Approach 2:
The patent optimizes various parameters of the lead frame leads including the slant angle, bend radius, lead thickness, and material composition. By carefully adjusting these parameters, the leads achieve low internal impedance while maintaining high electrical conductivity and mechanical strength.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves heat dissipation capabilities and reduces internal impedance, such as low source-drain impedance in MOSFETs, enabling efficient performance in applications like industrial power supplies and motor control systems.
Implementation Method 1
a heat sink located on the substrate
Implementation Method 2
a heat sink located on the substrate
Implementation Method 3
The bent portions of the second lead frame leads may be attached to the bottom surface of the substrate by a solder paste
Implementation Method 4
The solder resist layer may be attached to the bottom surface of the substrate by a solder adhesive or a polymeric adhesive
Data Source
AI summary
A semiconductor package device includes a lead frame including a lead frame pad and lead frame leads, a semiconductor chip located on the lead frame pad, and a substrate located on the semiconductor chip, wherein the lead frame leads include first lead frame leads coupled to the lead frame pad and second lead frame leads separated from the lead frame pad and attached to a bottom surface of the substrate.


