Semiconductor Package Layout for Low Parasitic Inductance
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Solution Overview
Problem
Existing semiconductor packages face challenges in reducing size while maintaining heat dissipation capability, parasitic inductance, voltage spikes, reliability performance, efficiency, and power density.
Innovation Solution
A semiconductor package design featuring a flipped low side FET attached to a lead frame, a metal clip connecting the low and high side FETs, and a molding encapsulation, with specific lead frame configurations to minimize parasitic inductance and enhance thermal dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the semiconductor package size is reduced, then the power density increases, but the parasitic inductance increases and heat dissipation capability deteriorates
Solution Approach 1:
The patent utilizes the Z-direction (vertical dimension) by flipping the low side FET and attaching it to the bottom surface of the lead frame, while the high side FET remains on the top surface. This three-dimensional arrangement reduces the planar footprint and package size while maintaining short current paths that minimize parasitic inductance. The direct connection of Lx leads to the end paddle in the vertical direction further exploits this dimensional approach.
Solution Approach 2:
The patent merges the low side FET and high side FET into a single compact package with integrated lead frame, eliminating the need for separate packages or PCB mounting. The metal clip combines both FETs and connects them to the lead frame, creating a unified structure that reduces overall size while maintaining electrical performance through optimized internal connections.
2Reliability
If the distance between low side FET and high side FET is reduced, then the parasitic inductance decreases, but the voltage spikes increase
Solution Approach 1:
The patent applies different structural configurations to different parts of the circuit: the Lx leads are directly connected to the end paddle with full thickness for low inductance, while the gate lead is positioned perpendicular to provide proper isolation. The metal clip provides localized clamping force and electrical connection at specific points, optimizing the balance between inductance reduction and voltage spike control in different regions of the package.
3Reliability
If the Lx leads are directly connected to the end paddle with full thickness, then the parasitic inductance decreases, but the manufacturing complexity increases
Solution Approach 1:
The lead frame is segmented into distinct functional zones: Vin leads for power input, Lx leads for switching node connections, gate lead for control, and end paddle for ground reference. Each segment is optimized for its specific function with appropriate thickness and routing, allowing the complex performance requirements to be achieved through modular design rather than a monolithic complex structure.
Data Source
AI summary
A semiconductor package includes a lead frame, a low side field-effect transistor (FET), a high side FET, a metal clip, and a molding encapsulation. The low side FET is flipped and is attached to a first die paddle of the lead frame. The lead frame comprises one or more voltage input (Vin) leads; a gate lead; one or more switching node (Lx) leads; a first die paddle; a second die paddle; and an end paddle. Each of an exposed bottom surface of the one or more Lx leads is directly connected to an exposed bottom surface of the end paddle. A longitudinal direction of an exposed bottom surface of the gate lead is perpendicular to a longitudinal direction of each of the exposed bottom surface of the one or more Lx leads. An entirely of each of the one or more Vin leads is of the full thickness.