Multi-Chip Semiconductor Package Layout for Low Parasitic Inductance
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Solution Overview
Problem
Semiconductor devices with multiple elements in a single package face challenges in reducing parasitic inductance and resistance, which hinders energy efficiency and responsiveness in electronic devices.
Innovation Solution
The semiconductor device configuration includes a conductive member with specific conductor connections and semiconductor elements, where the first conductor is connected to the source and drain electrodes of one element, the second conductor is connected to the source electrode of another element, and the third conductor is connected to the drain electrode, optimizing the electrical paths to minimize parasitic inductance and resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple semiconductor elements are integrated into a single resin package, then device functionality and compactness are improved, but parasitic inductance and parasitic resistance increase
Solution Approach 1:
The patent transitions from planar conductor arrangement to a three-dimensional stacked configuration. Conductors are arranged in multiple layers (first conductor layer, second conductor layer, third conductor layer) with vertical stacking, allowing current paths to be optimized in the vertical dimension rather than only horizontally. This reduces parasitic inductance by shortening current loop areas and reduces parasitic resistance by providing multiple parallel conduction paths.
Solution Approach 2:
The patent combines multiple conductors (first, second, and third conductors) and multiple semiconductor elements (first and second switching elements) into a single integrated package structure. The conductors are electrically connected to form continuous current paths that merge multiple functions into unified structures, reducing the number of external connections and associated parasitics.
2Ease of manufacture
If conventional conductor arrangements are used in multi-element packages, then manufacturing simplicity is maintained, but power consumption increases due to higher parasitic resistance
Solution Approach 1:
The patent segments the conductor system into distinct layers (first conductor layer with first and second conductors, third conductor layer with third conductor) that can be independently configured and manufactured. Each layer serves specific functional purposes, allowing optimized current paths for different circuit requirements while maintaining manufacturability through modular construction.
Solution Approach 2:
The patent changes the geometric parameters of the conductor arrangement by introducing vertical stacking and specific spatial relationships between conductors. The conductors are positioned at different heights and horizontal positions to minimize loop areas and optimize current distribution, directly reducing parasitic inductance and resistance without complicating the manufacturing process.
3Device complexity
If conventional conductor arrangements are used, then structural simplicity is maintained, but switching responsiveness deteriorates due to higher parasitic inductance
Solution Approach 1:
The patent introduces vertical dimension to conductor arrangement, creating a three-dimensional configuration that reduces current loop areas. The first conductor, second conductor, and third conductor are stacked vertically with optimized horizontal offsets, minimizing the area enclosed by current paths and thereby reducing parasitic inductance for faster switching responses.
Solution Approach 2:
The patent uses repetitive conductor patterns across multiple layers, with the first conductor layer and third conductor layer having similar structural configurations. This copying approach maintains structural simplicity while achieving performance improvement through the added vertical dimension, as the repeated patterns can be manufactured using standardized processes.
Data Source
AI summary
A semiconductor device includes a conductive member including first, second and third conductors mutually spaced, a first semiconductor element having a first obverse surface provided with a first drain electrode, a first source electrode and a first gate electrode, and a second semiconductor element having a second obverse surface provided with a second drain electrode, a second source electrode and a second gate electrode. The first conductor is electrically connected to the first source electrode and the second drain electrode. The second conductor is electrically connected to the second source electrode. As viewed in a first direction crossing the first obverse surface, the second conductor is adjacent to the first conductor in a second direction crossing the first direction. The third conductor is electrically connected to the first drain electrode and is adjacent to the first conductor and the second conductor as viewed in the first direction.