Direct-Contact Semiconductor Package for Low-Warpage Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor packages face challenges in achieving direct contact between wiring structures and semiconductor chips, leading to potential warpage and reduced reliability.
Innovation Solution
A semiconductor package design where a wiring structure is directly contacted by a semiconductor chip, with a connecting member between the structures and a mold layer isolating one surface of the chip from direct contact, enhancing process characteristics and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an interposer is used to electrically connect packages in POP type semiconductor packages, then electrical connection between upper and lower packages is facilitated and warpage is prevented, but the device complexity and package thickness increase
Solution Approach 1:
The patent removes the interposer component from the package structure and replaces it with a wiring structure that is directly formed on the semiconductor chip. This extraction of the interposer simplifies the overall package structure while maintaining the electrical connection function through direct wiring patterns on the chip surface.
Solution Approach 2:
The patent merges the functions of the interposer and the wiring structure into a single integrated wiring structure that is formed directly on the semiconductor chip. This combining of functions reduces the number of discrete components and simplifies the package architecture while achieving the same electrical connection objectives.
2Reliability
If an interposer is used in POP type semiconductor packages, then electrical connection and warpage prevention are achieved, but the package thickness increases
Solution Approach 1:
The patent extracts the interposer component from the package structure and replaces it with a wiring structure formed directly on the semiconductor chip, thereby eliminating the additional thickness that the interposer would contribute to the overall package height.
Solution Approach 2:
The patent transitions from a three-dimensional stacked structure with an interposer to a more planar configuration where wiring patterns are formed directly on the chip surface, reducing the vertical dimension and overall package thickness while maintaining electrical connectivity.
3Ease of manufacture
If wiring structures are not in direct contact with semiconductor chips, then manufacturing processes are simpler, but product reliability deteriorates
Solution Approach 1:
The patent performs preliminary actions by forming the wiring structure directly on the semiconductor chip during the chip fabrication process itself, before packaging. This preliminary integration ensures direct contact between the wiring structure and chip, improving reliability while maintaining manufacturing simplicity through process integration.
Data Source
AI summary
A semiconductor package includes a first wiring structure which includes a first insulating layer, and a first wiring pad inside the first insulating layer, a first semiconductor chip on the first wiring structure, a second wiring structure on the first semiconductor chip, and a connecting member between the first wiring structure and the second wiring structure. The second wiring structure includes a second insulating layer and a plurality of second wiring pads in the second insulating layer which each directly contact one surface of the first semiconductor chip.