Semiconductor Package Thermal Expansion-Matching Layer Warpage
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Solution Overview
Problem
The mismatch in thermal expansion coefficients between semiconductor chips, substrates, and encapsulation layers leads to warpage issues in flip chip package structures, causing poor contact and potential breakage of solder joints, which reduces the reliability of the package and poses challenges in high-temperature cycles.
Innovation Solution
Incorporating a thermal expansion-matching layer with a different thermal expansion coefficient than the encapsulation layer, which covers the top surface of the encapsulation layer and is flush with its side surface, to balance internal stress and prevent warpage, while also improving production efficiency by manufacturing in a panel type from a substrate to a wafer package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a flip chip package structure is assembled with chip, substrate and encapsulation layer, then electrical connection and protection are achieved, but warpage occurs due to CTE mismatch causing poor contact and solder joint breakage
Solution Approach 1:
A thermal expansion matching layer is introduced as an intermediary between the encapsulation layer and the chip/substrate assembly. This layer has a thermal expansion coefficient that matches the chip and substrate, serving as a mediator to balance the CTE mismatch between the encapsulation layer and the underlying components, thereby preventing warpage while maintaining the protective and electrical connection functions
Solution Approach 2:
The package structure is designed as a composite multi-layer system consisting of the chip, substrate, encapsulation layer, and thermal expansion matching layer. Each layer is selected with specific material properties, particularly thermal expansion coefficients, to create a composite structure that overall balances thermal stresses and prevents warpage during temperature cycling
2Productivity
If conventional individual package manufacturing is used, then each package is precisely assembled, but production efficiency is low and process time is long
Solution Approach 1:
Multiple individual packages are merged into a single panel-type manufacturing process. Instead of assembling and encapsulating each package separately, the invention processes multiple packages simultaneously on a panel, combining multiple assembly and encapsulation operations into one unified process flow, thereby dramatically improving production efficiency while maintaining assembly precision through standardized panel-level processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The thermal expansion-matching layer effectively balances the coefficient mismatch, preventing warpage and enhancing product yield, while reducing production time and improving the reliability of semiconductor package structures.
Implementation Method 1
The thermal expansion coefficient of the chip 12 is about 2.6 parts per million/Celsius (ppm/° C.), and the thermal expansion coefficient of the encapsulation layer 18 is about 10 ppm/° C. to 50 ppm/° C. The dis-match in coefficient of thermal expansion (CTE dis-match) amount the chip 12, the substrate 14 and the encapsulation layer 18 causes internal stress in the flip chip package structure 10
Data Source
AI summary
A semiconductor package structure includes a substrate, a chip, bumps, an encapsulation layer and a thermal expansion-matching layer. The chip is located on a top surface of the substrate. The bumps electrically connect the chip and the inner connection pads of the substrate. The encapsulation layer covers the bumps, the chip and the top surface of the substrate. The thermal expansion-matching layer covers the whole top surface of the encapsulation layer, and exposes the side surfaces of the encapsulation layer. The thermal expansion coefficient of the thermal expansion-matching layer is different from that of the encapsulation layer. The side surface of the thermal expansion-matching layer is flush with that of the encapsulation layer. The thermal expansion-matching layer balances the inner stresses caused by the difference of the thermal expansion. Thus, the invention reduces the warpage problem of the formed package.