Semiconductor Package Molding Layer Design for Thermal Stress Relief
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Solution Overview
Problem
Current semiconductor packages face challenges in reliability and durability due to thermal expansion mismatches and warpage issues, which can lead to cracks and poor electrical connections.
Innovation Solution
A semiconductor package design featuring an interposer substrate with a molding layer having a higher coefficient of thermal expansion than the semiconductor dies, strategically positioned to cover and expose specific sidewalls of the chips, and an under-fill layer to encapsulate bumps, thereby reducing stress and preventing cracks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a molding layer covers all sidewalls of semiconductor chips for protection, then reliability is improved, but thermal stress increases due to coefficient of thermal expansion mismatch
Solution Approach 1:
The molding layer is selectively applied to cover only specific sidewalls of the first semiconductor chip (first and third sidewalls) while leaving other sidewalls (second and fourth sidewalls) exposed. This local differentiation allows the package to gain protection where needed while minimizing thermal stress accumulation by exposing certain sidewalls to allow stress relief and thermal expansion/contraction.
2Duration of action of stationary object
If the molding layer completely encapsulates the semiconductor chip for protection, then durability is improved, but crack formation occurs due to restricted thermal expansion
Solution Approach 1:
By selectively exposing the second and fourth sidewalls of the semiconductor chip, the molding layer provides encapsulation and protection for critical areas while creating stress relief zones at the exposed sidewalls. This prevents crack formation by allowing the chip to expand and contract thermally without being completely constrained, thus improving durability.
3Reliability
If bonding wires are used to connect semiconductor chip to PCB, then electrical connection is achieved, but connection reliability is poor
Solution Approach 1:
The patent replaces the traditional bonding wire mechanical connection system with a bump-based electrical connection system. Conductive bumps are formed at the chip terminals and corresponding PCB pads, providing direct mechanical and electrical contact that is more reliable and stronger than thin bonding wires. This substitution eliminates the weak points associated with bonding wires while maintaining electrical connectivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances the reliability and compactness of the semiconductor package by reducing thermal stress, preventing cracks, and maintaining reliable electrical connections, while also preventing warpage of the interposer substrate.
Implementation Method 1
A molding layer having a higher coefficient of thermal expansion than the semiconductor dies
Data Source
AI summary
A semiconductor package includes a substrate and a first semiconductor chip on the substrate and having a first sidewall and a second sidewall different from the first sidewall. A second semiconductor chip is on the substrate and is laterally spaced apart from the first semiconductor chip. A molding layer is on the substrate and between the first sidewall of the first semiconductor chip and a sidewall of the second semiconductor chip. The molding layer exposes the second sidewall of the first semiconductor chip.