Semiconductor Package Structure With Multi-Level Redistribution Layers
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Solution Overview
Problem
The increasing miniaturization of semiconductor devices and the need for higher I/O contact pad density complicate packaging, leading to yield reduction due to the difficulty in managing and connecting a large number of contact pads in a small area.
Innovation Solution
A semiconductor package structure is developed using a temporary carrier and multiple redistribution layers, with a first chip having contact pads facing the carrier and a second chip with pads facing away, encapsulated to expose pads for connection, allowing for flexible chip orientation and optimized redistribution of connections for improved signal integrity and reduced warpage risk.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of I/O contact pads is increased to integrate more functions, then the functionality of semiconductor devices is improved, but the packaging difficulty increases and yield decreases
Solution Approach 1:
The patent transitions from a single-plane contact pad arrangement to a three-dimensional stacked configuration with multiple redistribution layers (RDLs) at different levels. This vertical dimensionality allows I/O contact pads to be distributed across multiple floors, reducing the density and complexity on any single packaging plane while maintaining high total I/O capacity.
Solution Approach 2:
The patent divides the I/O contact pad system into multiple segmented groups distributed across different redistribution layers and spatial locations. Instead of one large array of contact pads, the connections are segmented into multiple smaller arrays on different RDLs, making the packaging process more manageable and reducing the complexity of aligning and connecting all I/Os simultaneously.
2Area of moving object
If I/O contact pads are packed into smaller areas to reduce device size, then the miniaturization is achieved, but the density of contact pads increases and packaging becomes more difficult
Solution Approach 1:
The patent utilizes vertical stacking with multiple redistribution layers to distribute contact pads across three-dimensional space rather than compressing them into a single two-dimensional plane. This allows high I/O density to be achieved without proportionally increasing the lateral footprint, as connections are arranged in multiple vertical levels.
Solution Approach 2:
The patent implements a nested structure where multiple redistribution layers are stacked vertically, with each RDL containing subsets of contact pads and interconnects. The encapsulant further encloses these nested RDL structures, creating a compact hierarchical arrangement that reduces the overall device footprint while maintaining high I/O capacity.
Data Source
AI summary
A semiconductor package structure includes an encapsulant, a first chip, a second chip, a first redistribution layer and a second redistribution layer. The encapsulant has a first surface and a second surface opposite to each other. The first chip is in the encapsulant, wherein the first chip includes a plurality of contact pads exposed from the first surface of the encapsulant. The second chip is in the encapsulant, wherein second chip includes a plurality of contact pads exposed from the second surface of the encapsulant. The first redistribution layer is over the first surface of the encapsulant and electrically connected to the contact pads of the first chip. The second redistribution layer is over the second surface of the encapsulant and electrically connected to the contact pads of the second chip.