Semiconductor Package With Non-Integer Lead Pitches
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor packaging technologies face challenges in providing optimal electrical connections and mechanical attachment for high-voltage, high-current chips, particularly in preventing creepage current issues due to fixed lead pitches and widths, which are inadequate for varying voltage and current applications.
Innovation Solution
The use of packaged chips with leads having differing non-integer multiple lead pitches and widths, allowing for optimized lead configurations that accommodate varying current flows and voltage potentials, thereby enhancing electrical performance and preventing creepage current issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fixed lead pitches are used in semiconductor packaging, then manufacturing simplicity is maintained, but electrical performance is insufficient for high-voltage and high-current applications
Solution Approach 1:
The patent applies local quality by varying lead pitches and widths at different locations along the lead array. Specifically, the lead structure includes multiple pitch regions where the pitch between adjacent leads changes locally to match the electrical requirements of different chip regions, allowing optimal electrical performance for high-voltage and high-current applications without requiring complete redesign of the entire lead structure.
Solution Approach 2:
The patent implements parameter changes by transitioning from fixed lead pitches to variable lead pitches and widths. The lead structure incorporates multiple pitch values (e.g., first pitch, second pitch, third pitch) and varying lead widths within the same lead array, enabling the packaging to adapt to different electrical performance requirements across the chip surface.
2Reliability
If fixed lead widths and pitches are used, then device complexity is reduced, but the ability to prevent creepage current issues in high-voltage applications deteriorates
Solution Approach 1:
The patent addresses creepage current prevention by implementing local quality variations in lead spacing. High-voltage regions are assigned larger lead pitches to maintain adequate creepage distances, while low-voltage regions use smaller pitches. This localized adaptation of lead geometry ensures creepage current prevention where needed without unnecessarily increasing complexity throughout the entire device.
3Adaptability or versatility
If conventional packaging with uniform leads is used, then ease of manufacture is maintained, but adaptability to varying voltage and current applications is insufficient
Solution Approach 1:
The patent achieves adaptability through parameter changes in lead geometry. The lead array incorporates multiple pitch values and varying widths that can be configured to match different application requirements (high-voltage, high-current, signal processing). Despite this variability, the leads remain part of an integrated structure that can be manufactured using standard semiconductor packaging processes, balancing adaptability with manufacturability.
Data Source
AI summary
Packaged chips comprising non-integer lead pitches, systems and methods for manufacturing packaged chips are disclosed. In one embodiment a packaged device includes a first chip, a package encapsulating the first chip and a plurality of leads protruding from the package, wherein the plurality of leads comprises differing non-integer multiple lead pitches.