3D Passive Filter in Semiconductor Packages for Signal Integrity
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in maintaining signal integrity and power integrity as feature sizes shrink, particularly in effectively managing electromagnetic interference and heat dissipation while maintaining mechanical strength.
Innovation Solution
A semiconductor package design incorporating a three-dimensional passive filter with a ground plane, conductive patches, and inter-patch vias within a stack of polymer layers, which forms capacitors and inductors to create resonators that attenuate noise without increasing footprint, enhancing signal filtering and heat dissipation while improving mechanical strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional two-dimensional passive filter designs are used, then the footprint area is limited, but the filtering effectiveness and heat dissipation capability are insufficient
Solution Approach 1:
The patent transitions from conventional two-dimensional passive filter layouts to a three-dimensional configuration by stacking conductive layers (ground plane, power plane, signal plane) vertically within polymer layers. This dimensional change enables improved signal filtering and heat dissipation without increasing the horizontal footprint area, as the additional filtering capacity is achieved through vertical layering rather than horizontal expansion.
2Temperature
If more conductive materials are added to improve heat dissipation, then heat dissipation capability increases, but the device complexity increases
Solution Approach 1:
The patent integrates multiple functions into the passive filter structure: the stacked conductive layers (ground plane, power plane, signal plane) simultaneously provide electromagnetic shielding, signal filtering, and heat dissipation pathways. The conductive materials serve dual purposes of electrical connectivity and thermal management, reducing the need for separate heat dissipation components and thereby limiting the increase in device complexity.
3Productivity
If feature size is shrunk to improve integration density, then manufacturing capability improves, but signal integrity and power integrity deteriorate
Solution Approach 1:
The patent implements localized quality enhancement by creating vertically-stacked conductive regions with optimized electrical properties at specific locations within the semiconductor package. The three-dimensional passive filter structure provides localized electromagnetic shielding and signal routing pathways that maintain signal integrity even as overall feature dimensions are reduced, allowing high integration density without sacrificing reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves signal integrity, power integrity, and reduces electromagnetic interference while increasing the content of conductive materials for better heat dissipation and mechanical strength by utilizing a three-dimensional configuration of passive resonators.
Implementation Method 1
the conductive patches and the ground plane form capacitors with the polymer layer between the conductive patches and the ground plane
Implementation Method 2
the inter-patch vias and the conductive patches form inductors
Implementation Method 3
the inductors and the capacitors constitute passive resonators, and the periodically arranged passive resonators constitute a passive filter
Data Source
AI summary
A semiconductor package is provided. The semiconductor package includes a semiconductor die, a stack of polymer layers, redistribution elements and a passive filter. The polymer layers cover a front surface of the semiconductor die. The redistribution elements and the passive filter are disposed in the stack of polymer layers. The passive filter includes a ground plane and conductive patches. The ground plane is overlapped with the conductive patches, and the conductive patches are laterally separated from one another. The ground plane is electrically coupled to a reference voltage. The conductive patches are electrically connected to the ground plane, electrically floated, or electrically coupled to a direct current (DC) voltage.