3D Semiconductor Package Layout for Photonic Chip Integration
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Solution Overview
Problem
The challenge lies in developing semiconductor packages that integrate multiple devices, such as optical devices, while reducing size and weight, and ensuring structural, electrical, and optical characteristics meet high-performance requirements.
Innovation Solution
A semiconductor package design featuring a first substrate with distinct vertical levels, including a core portion with recess regions and vias for electrical connections, and optical waveguides for optical coupling, along with a cover portion for stability and thermal management, allowing for high integration density and reduced size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple semiconductor chips are integrated in a single package, then integration density increases, but package size and complexity increase
Solution Approach 1:
The patent transitions from planar integration to three-dimensional vertical integration by stacking semiconductor chips at different vertical levels. The first substrate has a top surface at a first vertical level and a bottom surface at a second vertical level, with chips mounted on both surfaces, enabling spatial utilization in the vertical dimension to increase integration density without proportionally increasing package footprint.
Solution Approach 2:
The patent implements a nested structure where the first substrate is disposed on the second substrate, and multiple chips are nested within the vertical space defined by the substrates. The first chip is mounted on the top surface of the first substrate, the second chip on the bottom surface, with vias penetrating through substrates to connect them, creating a compact nested arrangement that maximizes integration within minimal volume.
2Reliability
If vertical vias are used to electrically connect chips at different levels, then electrical connection is achieved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the electrical connection path into distinct vertical via components: first vias penetrate the first substrate to connect the first chip to the second substrate, while second vias penetrate the second substrate to connect to the second chip. This segmentation allows each via structure to be optimized independently and simplifies the overall manufacturing process by breaking down the complex inter-chip connection into manageable discrete elements.
3Volume of moving object
If chip size is reduced to decrease package size, then package compactness improves, but heat dissipation becomes more difficult
Solution Approach 1:
The patent introduces the first substrate and second substrate as intermediary thermal management structures between the mounted chips and the external environment. These substrates serve as thermal pathways that conduct heat away from the compactly arranged chips, enabling effective heat dissipation despite the reduced package size and increased integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves a compact semiconductor package with improved electrical characteristics and heat-dissipation efficiency, supporting high integration density and optical signal transmission.
Implementation Method 1
an optical waveguide on the first bottom surface... The optical waveguide extends toward the side surface of the core portion from a first region between the second semiconductor chip and the core portion to a second region beside the second semiconductor chip
Implementation Method 2
a first via vertically penetrating the first substrate and electrically connecting the first semiconductor chip to the second semiconductor chip
Data Source
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AI summary
A semiconductor package includes a first substrate having a first and second bottom surfaces located at different vertical levels from a top surface of the first substrate, a first semiconductor chip on the top surface of the first substrate, a second semiconductor chip on the first bottom surface and including a photonic integrated circuit, and a second substrate on the second bottom surface to cover the second semiconductor chip. The first substrate includes: a first via vertically penetrating the first substrate and electrically connecting the first semiconductor chip to the second semiconductor chip; a second via vertically penetrating the first substrate and electrically connecting the first semiconductor chip to the second substrate; and an optical waveguide on the first bottom surface. A first distance from the top surface to the first bottom surface is smaller than a second distance from the top surface to the second bottom surface.