Semiconductor Package Planarization for Fine Redistribution Patterns
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving compact size, low manufacturing cost, and efficient formation of fine patterns on redistribution substrates, particularly due to issues like delamination and step differences caused by copper pillars and protruding pads.
Innovation Solution
A semiconductor package design that includes a redistribution substrate with a semiconductor chip, a connection substrate, and a passivation and molding layer, where the passivation layers and dielectric layers are made of different materials, and a surface planarization process is used to ensure coplanarity, preventing delamination and enabling fine pattern formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If copper pillars and protruding pads are used for electrical connection, then electrical connectivity is improved, but delamination and step differences occur reducing reliability
Solution Approach 1:
The patent introduces a passivation layer as an intermediary between the copper pillar and the external environment, and a dielectric layer as an intermediary between the protruding pad and the molding layer. These intermediary layers prevent direct contact between incompatible materials, eliminating the delamination issue while maintaining electrical connectivity through the copper pillar and pad structures.
Solution Approach 2:
The patent changes the material parameters by using different materials for the passivation layer and dielectric layer than traditional single-material approaches. This material parameter change allows the structure to accommodate the copper pillar and protruding pad without generating harmful step differences, as the different materials have compatible thermal expansion and adhesion properties.
2Manufacturing precision
If fine patterns are formed on redistribution substrate, then device functionality is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent performs preliminary actions by forming the passivation layer and dielectric layer before final pattern formation. These preliminary layers provide a stable, planar foundation that simplifies subsequent fine pattern formation processes, reducing manufacturing complexity while enabling higher precision patterns on the redistribution substrate.
Solution Approach 2:
The patent changes surface parameters through the passivation and dielectric layers, creating an optimized surface for fine pattern formation. This parameter change in surface properties (flatness, adhesion, material composition) enables high-precision patterning while keeping the manufacturing process manageable by preventing defects that would require complex correction steps.
3Reliability
If different materials are used for passivation and dielectric layers, then delamination is prevented improving reliability, but material selection and processing complexity increases
Solution Approach 1:
The patent applies local quality by using different materials for the passivation layer and dielectric layer at different locations in the structure. Each layer is optimized for its specific function: the passivation layer protects the copper pillar, while the dielectric layer isolates the protruding pad. This localized material optimization prevents delamination while managing processing complexity through clear functional differentiation.
Data Source
AI summary
A semiconductor package includes a semiconductor chip on a redistribution substrate and including a body, a chip pad on the body, and a pillar on the chip pad, a connection substrate including base layers and a lower pad on a bottom surface of a lowermost one of the base layers, a first passivation layer between the semiconductor chip and the redistribution substrate, and a dielectric layer between the redistribution substrate and the connection substrate. The first passivation layer and the dielectric layer include different materials from each other. A bottom surface of the pillar, a bottom surface of the first passivation layer, a bottom surface of a molding layer, a bottom surface of the lower pad, and a bottom surface of the dielectric layer are coplanar with each other.